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- 09 7月, 2016 9 次提交
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由 Maxime Ripard 提交于
Introduce support for clocks that multiply and divide using linear factors. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-11-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Introduce support for clocks that use a combination of two linear multipliers. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-10-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Introduce support for the clocks that combine a linear divider and a power-of-two based one. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-9-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Add support for the various dividers (linear, table or pow-of-two based) found in the CCU. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-8-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Add support for the clocks in the CCU that introduce a phase shift from their parent clock. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-7-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Some clocks in the Allwinner SoCs clocks unit are just muxes. However, those muxes might also be found in some other complicated clocks that would benefit from the code in there to deal with "advanced" features, like pre-dividers. Introduce a set of helpers to reduce the code duplication in such cases. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-6-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Some clocks in the Allwinner SoCs clocks unit are just simple gates. Add support for those clocks. Since it's a feature that can also be found in more complex clocks, provide a bunch of helpers that can be reused later on. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-5-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Some clocks can be switched to a mode called fractional that have two fixed output rate you can choose from. Add a small library to deal with those clocks. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-4-maxime.ripard@free-electrons.com
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由 Maxime Ripard 提交于
Start our new clock infrastructure by adding the registration code, common structure and common code. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com
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- 28 5月, 2016 1 次提交
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由 Arnd Bergmann 提交于
Most users of IS_ERR_VALUE() in the kernel are wrong, as they pass an 'int' into a function that takes an 'unsigned long' argument. This happens to work because the type is sign-extended on 64-bit architectures before it gets converted into an unsigned type. However, anything that passes an 'unsigned short' or 'unsigned int' argument into IS_ERR_VALUE() is guaranteed to be broken, as are 8-bit integers and types that are wider than 'unsigned long'. Andrzej Hajda has already fixed a lot of the worst abusers that were causing actual bugs, but it would be nice to prevent any users that are not passing 'unsigned long' arguments. This patch changes all users of IS_ERR_VALUE() that I could find on 32-bit ARM randconfig builds and x86 allmodconfig. For the moment, this doesn't change the definition of IS_ERR_VALUE() because there are probably still architecture specific users elsewhere. Almost all the warnings I got are for files that are better off using 'if (err)' or 'if (err < 0)'. The only legitimate user I could find that we get a warning for is the (32-bit only) freescale fman driver, so I did not remove the IS_ERR_VALUE() there but changed the type to 'unsigned long'. For 9pfs, I just worked around one user whose calling conventions are so obscure that I did not dare change the behavior. I was using this definition for testing: #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \ unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO)) which ends up making all 16-bit or wider types work correctly with the most plausible interpretation of what IS_ERR_VALUE() was supposed to return according to its users, but also causes a compile-time warning for any users that do not pass an 'unsigned long' argument. I suggested this approach earlier this year, but back then we ended up deciding to just fix the users that are obviously broken. After the initial warning that caused me to get involved in the discussion (fs/gfs2/dir.c) showed up again in the mainline kernel, Linus asked me to send the whole thing again. [ Updated the 9p parts as per Al Viro - Linus ] Signed-off-by: NArnd Bergmann <arnd@arndb.de> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Andrew Morton <akpm@linux-foundation.org> Link: https://lkml.org/lkml/2016/1/7/363 Link: https://lkml.org/lkml/2016/5/27/486 Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 20 5月, 2016 1 次提交
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由 Maxime Ripard 提交于
The critical clock handling in __clk_core_init isn't taking the enable lock before calling clk_core_enable, which in turns triggers the warning in the lockdep_assert_held call in that function when lockep is enabled. Add the calls to clk_enable_lock/unlock to make sure it doesn't happen. Fixes: 32b9b109 ("clk: Allow clocks to be marked as CRITICAL") Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 17 5月, 2016 1 次提交
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由 Boris Brezillon 提交于
The PWM framework has clarified the concept of reference PWM config (the platform dependent config retrieved from the DT or the PWM lookup table) and real PWM state. Use pwm_get_args() when the PWM user wants to retrieve this reference config and not the current state. This is part of the rework allowing the PWM framework to support hardware readout and expose real PWM state even when the PWM has just been requested (before the user calls pwm_config/enable/disable()). Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NThierry Reding <thierry.reding@gmail.com>
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- 13 5月, 2016 4 次提交
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由 Purna Chandra Mandal 提交于
This clock driver implements PIC32 specific clock-tree. clock-tree entities can only be configured through device-tree file (OF). Signed-off-by: NPurna Chandra Mandal <purna.mandal@microchip.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-clk@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13247/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Archit Taneja 提交于
The branch clocks MMSS_MMAGIC_AXI_CLK and MMAGIC_BIMC_AXI_CLK are controlled by RPM when the APPs processor enable or disable the RPM_MMAXI_CLK. During the boot sequence, someone can enable the RPM_MMAXI_CLK, resulting in register status bits showing that these clocks are enabled, our clock driver may look at the enabled status of these clocks and try to disable them since it thinks they are unused. Don't make the clock driver touch these clocks. Signed-off-by: NArchit Taneja <architt@codeaurora.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Harvey Hunt 提交于
The JZ4780's MSC clock divider registers multiply the clock divider by 2. This means that MMC devices run at half their expected speed. Add the ability to divide the clock divider in order to solve this. Signed-off-by: NHarvey Hunt <harvey.hunt@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Maxime Ripard 提交于
The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend), that have a lot in common with the clock to drive the first TCON channel. Add a driver to support both. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Acked-by: NRob Herring <robh@kernel.org> [sboyd@codeaurora.org: Silence variable sized array warning] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 09 5月, 2016 4 次提交
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由 Heiko Stuebner 提交于
Previously when everything happened in the set_rate callbacks itself we needed the old_rate value for the possible rate rollback, so that made it easy to also use it in the debug output. Now with the param-handling being done in separate functions, reading and recalculating the current pll rate only to use it in a debug message that won't get displayed in regular cases anyway is quite a waste. Therefore drop that value from the debug output. In the worst case that previous rate will have been displayed on the rate change before. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Heiko Stuebner 提交于
With the previous commit, the clock drivers now know at init time if the GRF regmap is available. That means if it isn't available then, it also won't become available later and we can therefore switch PLLs, that need the GRF for the lock-status, to read-only mode - similar behaviour as the aborting of rate changes we did before. This saves some conditionals on every rate change and we can also drop the rockchip_clk_get_grf function completely. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Heiko Stuebner 提交于
In the distant past syscons were initialized pretty late and weren't available at the time the clock init ran. As the GRF is mainly needed for PLL lock-status checking, we had this lazy init that tried to grab the syscon on PLL rate changes and denied these changes if it was not available. These days syscons are available very early and recent addition to rockchip clocks, like the PLL clk_init actually also rely on them being available at that time, so there is no need to keep that lazy init around, as it will also result in some more simplifications in other parts of the clock-code. Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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由 Douglas Anderson 提交于
The rk3399 clock table had a simple typo in it, calling the SDMMC sample and drive clocks by the wrong name. Fix this minor typo. Signed-off-by: NDouglas Anderson <dianders@chromium.org> Tested-by: NBrian Norris <briannorris@chromium.org> Acked-by: NBrian Norris <briannorris@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 07 5月, 2016 9 次提交
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由 Thomas Petazzoni 提交于
The Armada CP110 system controller provides, amongst other things, a number of clocks for the platform: a small number of core clocks, and then a number of gatable clocks, derived from some of the core clocks. Those clocks are configured via registers of the CP110 System Controller. The CP110 is the other core HW block (next to the AP806) used in the Marvel Armada 7K and 8K SoCs. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Thomas Petazzoni 提交于
The Armada AP806 system controller, amongst other things, provides a number of clocks for the platform: the CPU cluster clocks, whose frequencies are found by reading the Sample At Reset register, one fixed clock, and another clock derived from the fixed clock, which is the one used by most peripherals in AP806. The AP806 is one of the two core HW blocks used in the Marvell 7K/8K SoCs. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> [sboyd@codeaurora.org: Silence some checkpatch noise] Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Jiancheng Xue 提交于
The CRG(Clock and Reset Generator) block provides clock and reset signals for other modules in hi3519 soc. Signed-off-by: NJiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Jiancheng Xue 提交于
Change some arguments to constant type. Export some hisilicon APIs to modules. Signed-off-by: NJiancheng Xue <xuejiancheng@huawei.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Jiancheng Xue 提交于
In most of hisilicon SOCs, reset controller and clock provider are combined together as a block named CRG (Clock and Reset Generator). This patch mainly implements the reset function. Signed-off-by: NJiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Vaishali Thakkar 提交于
When sizeof is applied to a pointer typed expression, it gives the size of the pointer. So, here do not use sizeof on pointer type. Also, silent checkpatch.pl by using kmalloc_array over kmalloc. Note that this has no effect on runtime because 'parent_names' is a pointer to a pointer. Problem found using Coccinelle. Signed-off-by: NVaishali Thakkar <vaishali.thakkar@oracle.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Andy Gross 提交于
This patch adds the CLK_SET_RATE_PARENT flag for the crypto core and ahb blocks. Without this flag, clk_set_rate can fail for certain frequency requests. Signed-off-by: NAndy Gross <andy.gross@linaro.org> Fixes: 3966fab8 ("clk: qcom: Add MSM8916 Global Clock Controller support") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Stephen Boyd 提交于
Failure to initialize this flag to 0 by default can result in stack junk filling the clk_init_data structure and weird things happen. Joachim noticed that the critical clk feature started triggering for these clks causing boot failures, when it really shouldn't have happened: BUG: scheduling while atomic: swapper/0/0x00000002 CPU: 0 PID: 0 Comm: swapper Not tainted 4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826 Hardware name: NXP LPC18xx/43xx (Device Tree) [<2800be81>] (unwind_backtrace) from [<2800b22f>] (show_stack+0xb/0xc) [<2800b22f>] (show_stack) from [<2801ea21>] (__schedule_bug+0x2d/0x44) [<2801ea21>] (__schedule_bug) from [<281dc937>] (__schedule+0x3b/0x268) [<281dc937>] (__schedule) from [<281dcbbb>] (schedule+0x57/0x64) [<281dcbbb>] (schedule) from [<281de8ef>] (schedule_timeout+0xfb/0x120) [<281de8ef>] (schedule_timeout) from [<28030fcd>] (msleep+0xf/0x12) [<28030fcd>] (msleep) from [<28165a6d>] (clk_creg_32k_prepare+0x1f/0x24) [<28165a6d>] (clk_creg_32k_prepare) from [<281620d5>] (clk_core_prepare+0x1d/0x36) [<281620d5>] (clk_core_prepare) from [<2816340b>] (clk_register+0x22f/0x318) [<2816340b>] (clk_register) from [<282b06c9>] (lpc18xx_creg_clk_init+0x55/0x84) [<282b06c9>] (lpc18xx_creg_clk_init) from [<282b0149>] (of_clk_init+0xc1/0x12c) [<282b0149>] (of_clk_init) from [<282a665d>] (time_init+0x15/0x20) [<282a665d>] (time_init) from [<282a457d>] (start_kernel+0x169/0x274) [<282a457d>] (start_kernel) from [<28008025>] (0x28008025) bad: scheduling from the idle thread! CPU: 0 PID: 0 Comm: swapper Tainted: G W 4.6.0-rc6-next-20160505-00001-g5c8320450d1c #826 Fix this by initializing the flags member to 0. Acked-by: NJoachim Eastwood <manabian@gmail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Jose Abreu 提交于
The ARC SDP I2S clock can be programmed using a specific PLL. This patch has the goal of adding a clock driver that programs this PLL. At this moment the rate values are hardcoded in a table but in the future it would be ideal to use a function which determines the PLL values given the desired rate. Signed-off-by: NJose Abreu <joabreu@synopsys.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 06 5月, 2016 3 次提交
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由 Philipp Zabel 提交于
The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m, but is routed out of the HDMI PHY module. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Acked-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Philipp Zabel 提交于
The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Acked-by: NJames Liao <jamesjj.liao@mediatek.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Philipp Zabel 提交于
This mux is supposed to select a fitting divider after the PLL is already set to the correct rate. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Acked-by: NJames Liao <jamesjj.liao@mediatek.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org>
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- 03 5月, 2016 2 次提交
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由 Stefan Agner 提交于
The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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由 Masahiro Yamada 提交于
Unlike devm_clk_register(), devm_clk_hw_register() returns integer. So, the statement "Clocks returned from this function ..." sounds odd. Adjust the comment for this new API. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 28 4月, 2016 6 次提交
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由 Thierry Reding 提交于
Increase the readability of the CVB frequency table by reformatting it a little. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Upon failure to probe the DFLL, the OPP table will not be cleaned up properly. Fix this and while at it make sure the OPP table will also be cleared upon driver removal. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Rename some variables and structure fields to make the code more comprehensible. Also change the prototype of internal functions to be more in line with the OPP core functions. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
Instead of copying parts of the CVB table into a separate structure, keep track of the selected CVB table and directly reference data from it. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Thierry Reding 提交于
The kerneldoc for struct tegra_dfll_soc_data is stale. Update it to match the current structure definition. Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Lucas Stach 提交于
The post divider value in the frequency table is wrong as it would lead to the PLL producing an output rate of 960 MHz instead of the desired 480 MHz. This wasn't a problem as nothing used the table to actually initialize the PLL rate, but the bootloader configuration was used unaltered. If the bootloader does not set up the PLL it will fail to come when used under Linux. To fix this don't rely on the bootloader, but set the correct rate in the clock driver. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NThierry Reding <treding@nvidia.com>
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