- 02 3月, 2011 3 次提交
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由 Chris Wilson 提交于
Using PM latency request turns out to be very fragile and only works for some systems, depending upon the ACPI implementation. However, I've stumbled across a promising bit in INSTPM: "Interrupt-Based AGPBUSY#". This reverts commit b0b544cd. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Userspace has a legitimate requirement to use a delta that points to outside of the target bo, and so we need to enable this. (As this is an abi break, albeit a relaxation of the current restrictions, mark the change with a new flag.) Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
drivers/gpu/drm/i915/i915_irq.c: In function ‘ironlake_irq_postinstall’: drivers/gpu/drm/i915/i915_irq.c:1618: warning: unused variable ‘pipe’ Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 25 2月, 2011 1 次提交
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 22 2月, 2011 11 次提交
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由 Chris Wilson 提交于
In order to prevent "crushed blacks" on TVs, the range of the RGB output may be limited to 16-235. This used to be available through Xorg under the "Broadcast RGB" option, so reintroduce support for KMS. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34543Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
The code paths for modesetting are growing in complexity as we may need to move the buffers around in order to fit the scanout in the aperture. Therefore we face a choice as to whether to thread the interruptible status through the entire pinning and unbinding code paths or to add a flag to the device when we may not be interrupted by a signal. This does the latter and so fixes a few instances of modesetting failures under stress. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
As we just need a temporary array whilst performing the relocations for the execbuffer, first attempt to allocate using kmalloc even if it is not of order page-0. This avoids the overhead of remapping the discontiguous array and so gives a moderate boost to execution throughput. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Seems like we are forever to be cursed with buggy firmware, so allow the user to explicitly set the panel connection status. Of secondary utility for cases where I run laptops with the lid closed, but still want to configure the LVDS. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Dave Airlie spotted that we had a potential bug should we ever rearrange the drm_i915_gem_object so not the base drm_gem_object was not its first member. He noticed that we often convert the return of drm_gem_object_lookup() immediately into drm_i915_gem_object and then check the result for nullity. This is only valid when the base object is the first member and so the superobject has the same address. Play safe instead and use the compiler to convert back to the original return address for sanity testing. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Jesse Barnes 提交于
In a few places I replaced reads of per-pipe registers with the actual register offsets themselves (converting I915_READ(reg) to _PIPE(reg)). Alexey caught this on his 9xx machine because the cursor control write was affected. A quick audit showed a few more places where I'd borked a read, so here's a patch to fix things up. Reported-by: NAlexey Fisher <bug-track@fisher-privat.net> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> [ickle: compilation fix] Tested-by: NAlexey Fisher <bug-track@fisher-privat.net> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
This reverts commit 633f2ea2 and the attempted fix dcbe6f2b. There is a single clock source used for both SSC (some LVDS and DP) and non-SSC (VGA, DVI) outputs. So we need to be careful to only enable SSC as necessary. However, fiddling with DREFCLK was causing DP links to be dropped and we do not have a fix ready, so revert. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Jesse Barnes 提交于
eDP on the CPU doesn't need the PCH set up at all, it can in fact cause problems. So avoid FDI training and PCH PLL enabling in that case. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NAndy Whitcroft <apw@canonical.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Jesse Barnes 提交于
We can enable some safely, but FDI and transcoder interrupts can occur and block other interrupts from being detected (like port hotplug events). So keep them disabled by default (they can be re-enabled for debugging display bringup, but should generally be off). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
If the gpu is hung, then whatever was inside the render cache is lost and there is little point waiting for it. Or complaining if we see an EIO or EAGAIN instead. So, if the GPU is indeed in its death throes when we need to rewrite the registers for a new framebuffer, just ignore the error and proceed with the update. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Indan Zupancic 提交于
The current code does not follow Intel documentation: It misses some things and does other, undocumented things. This causes wrong backlight values in certain conditions. Instead of adding tricky code handling badly documented and rare corner cases, don't handle combination mode specially at all. This way PCI_LBPC is never touched and weird things shouldn't happen. If combination mode is enabled, then the only downside is that changing the brightness has a greater granularity (the LBPC value), but LBPC is at most 254 and the maximum is in the thousands, so this is no real functional loss. A potential problem with not handling combined mode is that a brightness of max * PCI_LBPC is not bright enough. However, this is very unlikely because from the documentation LBPC seems to act as a scaling factor and doesn't look like it's supposed to be changed after boot. The value at boot should always result in a bright enough screen. IMPORTANT: However, although usually the above is true, it may not be when people ran an older (2.6.37) kernel which messed up the LBPC register, and they are unlucky enough to have a BIOS that saves and restores the LBPC value. Then a good kernel may seem to not work: Max brightness isn't bright enough. If this happens people should boot back into the old kernel, set brightness to the maximum, and then reboot. After that everything should be fine. For more information see the below links. This fixes bugs: http://bugzilla.kernel.org/show_bug.cgi?id=23472 http://bugzilla.kernel.org/show_bug.cgi?id=25072Signed-off-by: NIndan Zupancic <indan@nul.nu> Tested-by: NAlex Riesen <raa.lkml@gmail.com> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 17 2月, 2011 9 次提交
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由 Alex Deucher 提交于
The fixed ref/post dividers are set by the AdjustPll table rather than the ss info table on dce4+. Make sure we enable the fractional feedback dividers when using a fixed post or ref divider on them as well. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=29272Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Marek Olšák 提交于
Signed-off-by: NMarek Olšák <maraeo@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Ben Skeggs 提交于
This has been broken since 2.6.37, and fixes resume on a couple of fermi boards I have access to. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
We free the temporary binding before leaving this function, so we also have to wait for the move to actually complete. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
Due to the default case handling the older chipsets, a bunch of the newer ones ended up having the wrong tiling regs used. This commit switches the default case to handle the newest chipsets. This also makes nv4e touch the "extra" tiling regs. "nv" doesn't touch them for C51 but traces of the NVIDIA binary driver show it being done there. I couldn't find NV41/NV45 traces to confirm the behaviour there, but an educated guess was taken at each of them. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Ben Skeggs 提交于
The DRM core fills this value, but at too late a stage for this to work, possibly resulting in an undesirable mode being selected. Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Francisco Jerez 提交于
Signed-off-by: NFrancisco Jerez <currojerez@riseup.net> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Francisco Jerez 提交于
Reported-by: NAlex Buell <alex.buell@munted.org.uk> Signed-off-by: NFrancisco Jerez <currojerez@riseup.net> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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由 Francisco Jerez 提交于
Reported-by: NAlex Buell <alex.buell@munted.org.uk> Signed-off-by: NFrancisco Jerez <currojerez@riseup.net> Signed-off-by: NBen Skeggs <bskeggs@redhat.com>
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- 16 2月, 2011 3 次提交
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由 Chris Wilson 提交于
Share the lid detection code for the all panels for consistent behaviour and a single place to add the eventual quirks for crap hardware. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Jesse Barnes 提交于
We can enable some safely, but FDI and transcoder interrupts can occur and block other interrupts from being detected (like port hotplug events). So keep them disabled by default (they can be re-enabled for debugging display bringup, but should generally be off). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
If the gpu is hung, then whatever was inside the render cache is lost and there is little point waiting for it. Or complaining if we see an EIO or EAGAIN instead. So, if the GPU is indeed in its death throes when we need to rewrite the registers for a new framebuffer, just ignore the error and proceed with the update. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 15 2月, 2011 3 次提交
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由 Alex Deucher 提交于
The problematic boards have a recommended reference divider to be used when spread spectrum is enabled on the laptop panel. Enable the use of the recommended reference divider along with the new pll algo. v2: testing options v3: When using the fixed reference divider with LVDS, prefer min m to max p and use fractional feedback dividers. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28852 https://bugzilla.kernel.org/show_bug.cgi?id=24462 https://bugzilla.kernel.org/show_bug.cgi?id=26552 MacbookPro issues reported by Justin Mattock <justinmattock@gmail.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Prevent divider overflow. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28932Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 14 2月, 2011 10 次提交
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由 Alex Deucher 提交于
Makes debugging CS rejections much easier. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Marek Olšák 提交于
This is an important security fix because we allowed arbitrary values to be passed to AARESOLVE_OFFSET. This also puts the right buffer address in the register. Signed-off-by: NMarek Olšák <maraeo@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Marek Olšák 提交于
Also move ZB_DEPTHCLEARVALUE to the list of safe regs. Signed-off-by: NMarek Olšák <maraeo@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Not only is linear aligned supposedly more performant, linear general is only supported by the CB in single slice mode. The texture hardware doesn't support linear general, but I think the hw automatically upgrades it to linear aligned. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Not only is linear aligned supposedly more performant, linear general is only supported by the CB in single slice mode. The texture hardware doesn't support linear general, but I think the hw automatically upgrades it to linear aligned. Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Dave Airlie 提交于
My evergreen has been in a remote PC for week and reset has never once saved me from certain doom, I finally relocated to the box with a serial cable and noticed an oops when the GPU resets, and the TTM delayed delete thread tries to remove something from the GTT. This stops the delayed delete thread from executing across the GPU reset handler, and woot I can GPU reset now. Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Alex Deucher 提交于
Based on 6xx/7xx endian fixes from Cédric Cano. v2: fix typo in shader Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Cédric Cano 提交于
agd5f: minor cleanups Signed-off-by: NCédric Cano <ccano@interfaceconcept.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Cédric Cano 提交于
agd5f: additional cleanups/fixes Signed-off-by: NCédric Cano <ccano@interfaceconcept.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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由 Cédric Cano 提交于
agd5f: minor cleanups Signed-off-by: NCédric Cano <ccano@interfaceconcept.com> Signed-off-by: NAlex Deucher <alexdeucher@gmail.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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