1. 26 8月, 2009 1 次提交
    • S
      davinci: EDMA: multiple CCs, channel mapping and API changes · 60902a2c
      Sudhakar Rajashekhara 提交于
      - restructure to support multiple channel controllers by using
        additional struct resources for each CC
      
      - interface changes visible to EDMA clients
      
        Introduce macros to build IDs from controller and channel number,
        and to extract them. Modify the edma_alloc_slot function to take an
        extra argument for the controller.
      
        Also update ASoC drivers to use API.  ASoC changes
      Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      
      - Move queue related mappings to dm<soc>.c
      
        EDMA in DM355 and DM644x has two transfer controllers while DM646x
        has four transfer controllers. Moving the queue to tc mapping and
        queue priority mapping to dm<soc>.c will be helpful to probe these
        mappings from platform device so that the machine_is_* testing will
        be avoided.
      
      - add channel mapping logic
      
        Channel mapping logic is introduced in dm646x EDMA. This implies
        that there is no fixed association for a channel number to a
        parameter entry number. In other words, using the DMA channel
        mapping registers (DCHMAPn), a PaRAM entry can be mapped to any
        channel. While in the case of dm644x and dm355 there is a fixed
        mapping between the EDMA channel and Param entry number.
      Signed-off-by: NNaresh Medisetty <naresh@ti.com>
      Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
      Reviewed-by: NDavid Brownell <dbrownell@users.sourceforge.net>
      Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      60902a2c
  2. 15 5月, 2009 1 次提交
    • D
      ASoC: davinci-pcm buildfixes · 82075af6
      David Brownell 提交于
      This is a buildfix for the DaVinci PCM code, resyncing it with
      the version in the DaVinci tree.  The notable change is using
      current EDMA interfaces, which recently merged to mainline.
      (The older interfaces never made it into mainline.)
      
      NOTE:  open issue, the DMA should be to/from SRAM; see chip
      errata for more info.  The artifacts are extremely easy to
      hear on DM355 hardware (not yet supported in mainline), but
      don't seem as audible on DM6446 hardwaare (which does have
      mainline support).
      Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
      Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      82075af6
  3. 20 1月, 2009 1 次提交
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  10. 24 4月, 2008 1 次提交