1. 27 4月, 2008 3 次提交
  2. 21 4月, 2008 9 次提交
    • A
      PCI: pci_scan_device() mustn't be __devinit · 7f7b5de2
      Adrian Bunk 提交于
      WARNING: drivers/pci/built-in.o(.text+0x150f): Section mismatch in reference from the function pci_scan_single_device() to the function .devinit.text:pci_scan_device()
      Signed-off-by: NAdrian Bunk <bunk@kernel.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      7f7b5de2
    • A
      PCI: pci_alloc_child_bus() mustn't be __devinit · cbd4e055
      Adrian Bunk 提交于
      WARNING: drivers/pci/built-in.o(.text+0xc4c): Section mismatch in reference from the function pci_add_new_bus() to the function .devinit.text:pci_alloc_child_bus()
      Signed-off-by: NAdrian Bunk <bunk@kernel.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      cbd4e055
    • I
      PCI: clean up resource alignment management · 88452565
      Ivan Kokshaysky 提交于
      Done per Linus' request and suggestions. Linus has explained that
      better than I'll be able to explain:
      
      On Thu, Mar 27, 2008 at 10:12:10AM -0700, Linus Torvalds wrote:
      > Actually, before we go any further, there might be a less intrusive
      > alternative: add just a couple of flags to the resource flags field (we
      > still have something like 8 unused bits on 32-bit), and use those to
      > implement a generic "resource_alignment()" routine.
      >
      > Two flags would do it:
      >
      >  - IORESOURCE_SIZEALIGN: size indicates alignment (regular PCI device
      >    resources)
      >
      >  - IORESOURCE_STARTALIGN: start field is alignment (PCI bus resources
      >    during probing)
      >
      > and then the case of both flags zero (or both bits set) would actually be
      > "invalid", and we would also clear the IORESOURCE_STARTALIGN flag when we
      > actually allocate the resource (so that we don't use the "start" field as
      > alignment incorrectly when it no longer indicates alignment).
      >
      > That wouldn't be totally generic, but it would have the nice property of
      > automatically at least add sanity checking for that whole "res->start has
      > the odd meaning of 'alignment' during probing" and remove the need for a
      > new field, and it would allow us to have a generic "resource_alignment()"
      > routine that just gets a resource pointer.
      
      Besides, I removed IORESOURCE_BUS_HAS_VGA flag which was unused for ages.
      Signed-off-by: NIvan Kokshaysky <ink@jurassic.park.msu.ru>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Gary Hade <garyhade@us.ibm.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      88452565
    • B
      PCI: Expose PCI VPD through sysfs · 94e61088
      Ben Hutchings 提交于
      Vital Product Data (VPD) may be exposed by PCI devices in several
      ways.  It is generally unsafe to read this information through the
      existing interfaces to user-land because of stateful interfaces.
      
      This adds:
      - abstract operations for VPD access (struct pci_vpd_ops)
      - VPD state information in struct pci_dev (struct pci_vpd)
      - an implementation of the VPD access method specified in PCI 2.2
        (in access.c)
      - a 'vpd' binary file in sysfs directories for PCI devices with VPD
        operations defined
      
      It adds a probe for PCI 2.2 VPD in pci_scan_device() and release of
      VPD state in pci_release_dev().
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      94e61088
    • S
      PCI: add PCI Express ASPM support · 7d715a6c
      Shaohua Li 提交于
      PCI Express ASPM defines a protocol for PCI Express components in the D0
      state to reduce Link power by placing their Links into a low power state
      and instructing the other end of the Link to do likewise. This
      capability allows hardware-autonomous, dynamic Link power reduction
      beyond what is achievable by software-only controlled power management.
      However, The device should be configured by software appropriately.
      Enabling ASPM will save power, but will introduce device latency.
      
      This patch adds ASPM support in Linux. It introduces a global policy for
      ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control
      it. The interface can be used as a boot option too. Currently we have
      below setting:
              -default, BIOS default setting
              -powersave, highest power saving mode, enable all available ASPM
      state and clock power management
              -performance, highest performance, disable ASPM and clock power
      management
      By default, the 'default' policy is used currently.
      
      In my test, power difference between powersave mode and performance mode
      is about 1.3w in a system with 3 PCIE links.
      
      Note: some devices might not work well with aspm, either because chipset
      issue or device issue. The patch provide API (pci_disable_link_state),
      driver can disable ASPM for specific device.
      Signed-off-by: NShaohua Li <shaohua.li@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      7d715a6c
    • G
      PCI: Include PCI domain in PCI bus names on x86/x86_64 · cb3576fa
      Gary Hade 提交于
      The PCI bus names included in /proc/iomem and /proc/ioports are
      of the form 'PCI Bus #XX' where XX is the bus number.  This patch
      changes the naming to 'PCI Bus XXXX:YY' where XXXX is the domain
      number and YY is the bus number.  For example, PCI bus 14 in
      domain 0 will show as 'PCI Bus 0000:14' instead of 'PCI Bus #14'.
      This change makes the naming consistent with other architectures
      such as ia64 where multiple PCI domain support has been around
      longer.
      Signed-off-by: NGary Hade <garyhade@us.ibm.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      cb3576fa
    • G
      PCI: remove global list of PCI devices · 5ff580c1
      Greg Kroah-Hartman 提交于
      This patch finally removes the global list of PCI devices.  We are
      relying entirely on the list held in the driver core now, and do not
      need a separate "shadow" list as no one uses it.
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      5ff580c1
    • G
      PCI: add is_added flag to struct pci_dev · 8a1bc901
      Greg Kroah-Hartman 提交于
      This lets us check if the device is really added to the driver core or
      not, which is what we need when walking some of the bus lists.  The flag
      is there in anticipation of getting rid of the other PCI device list,
      which is what we used to check in this situation.
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      8a1bc901
    • G
      PCI: make no_pci_devices() use the pci_bus_type list · 70308923
      Greg Kroah-Hartman 提交于
      no_pci_devices() should use the driver core list of PCI devices, not our
      "separate" one.
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      70308923
  3. 20 4月, 2008 1 次提交
  4. 05 3月, 2008 1 次提交
    • S
      PCI: fix section mismatch warning in pci_scan_child_bus · 0ab2b57f
      Sam Ravnborg 提交于
      Fix following warning:
      WARNING: vmlinux.o(.text+0x47bdb1): Section mismatch in reference from the function pci_scan_child_bus() to the function .devinit.text:pcibios_fixup_bus()
      
      We had plenty of functions that could be annotated __devinit but due to
      the former restriction that exported symbols could not be annotated
      they were not so.  So annotate these function and fix the references
      from the pci/hotplug/* code to silence the resuting warnings.
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      0ab2b57f
  5. 06 2月, 2008 2 次提交
  6. 03 2月, 2008 3 次提交
    • S
      PCI: fix 4x section mismatch warnings · 451124a7
      Sam Ravnborg 提交于
      The following warnings were issued during build of
      drivers/pci with an allyesconfig build:
      WARNING: o-x86_64/drivers/pci/built-in.o(.text+0xdaf): Section mismatch in reference from the function pci_add_new_bus() to the function .devinit.text:pci_alloc_child_bus()
      WARNING: o-x86_64/drivers/pci/built-in.o(.text+0x15e2): Section mismatch in reference from the function pci_scan_single_device() to the function .devinit.text:pci_scan_device()
      WARNING: o-x86_64/drivers/pci/built-in.o(.text+0x1b0c5): Section mismatch in reference from the function pci_bus_assign_resources() to the function .devinit.text:pci_setup_bridge()
      WARNING: o-x86_64/drivers/pci/built-in.o(.text+0x1b32d): Section mismatch in reference from the function pci_bus_size_bridges() to the function .devinit.text:pci_bus_size_cardbus()
      
      Investigating each case closer it looked like all
      referred functions are only used in the init phase
      or during hotplug.
      So to avoid wasting too much memory in the non-hotplug
      case the simpler fix was to allow the fuctions to
      use code/data from the __devinit sections.
      This was done in all four case by adding the __ref
      annotation.
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      Cc: Adrian Bunk <bunk@kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      451124a7
    • S
      PCI: fix section mismatch warnings referring to pci_do_scan_bus · 4105717b
      Sam Ravnborg 提交于
      Fix following warnings:
      WARNING: o-x86_64/drivers/pci/built-in.o(.text+0xb054): Section mismatch in reference from the function cpci_configure_slot() to the function .devinit.text:pci_do_scan_bus()
      WARNING: o-x86_64/drivers/pci/built-in.o(.text+0x153ab): Section mismatch in reference from the function shpchp_configure_device() to the function .devinit.text:pci_do_scan_bus()
      WARNING: o-x86_64/drivers/pci/built-in.o(__ksymtab+0xc0): Section mismatch in reference from the variable __ksymtab_pci_do_scan_bus to the function .devinit.text:pci_do_scan_bus()
      
      PCI hotplug were the only user of pci_do_scan_bus()
      so moving this function to a separate file that is build
      only when we enable CONFIG_HOTPLUG_PCI.
      Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
      Cc: Adrian Bunk <bunk@kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      4105717b
    • G
      Revert "PCI: PCIE ASPM support" · cc3a1378
      Greg Kroah-Hartman 提交于
      This reverts commit 6c723d5b.
      
      It caused build errors on non-x86 platforms, config file confusion, and
      even some boot errors on some x86-64 boxes.  All around, not quite ready
      for prime-time :(
      
      Cc: Shaohua Li <shaohua.li@intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      cc3a1378
  7. 02 2月, 2008 6 次提交
  8. 25 1月, 2008 1 次提交
    • G
      driver core: add way to get to bus device klist · b249072e
      Greg Kroah-Hartman 提交于
      This allows an easier way to get to the device klist associated with a
      struct bus_type (you have three to choose from...)  This will make it
      easier to move these fields to be dynamic in a future patch.
      
      The only user of this is the PCI core which horribly abuses this
      interface to rearrange the order of the pci devices.  This should be
      done using the existing bus device walking functions, but that's left
      for future patches.
      
      Cc: Kay Sievers <kay.sievers@vrfy.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b249072e
  9. 28 12月, 2007 1 次提交
    • L
      [PCI] Do not enable CRS Software Visibility by default · ad7edfe0
      Linus Torvalds 提交于
      It appears that some PCI-E bridges do the wrong thing in the presense of
      CRS Software Visibility and MMCONFIG.  In particular, it looks like an
      ATI bridge (device ID 7936) will return 0001 in the vendor ID field of
      any bridged devices indefinitely.
      
      Not enabling CRS SV avoids the problem, and as we currently do not
      really make good use of the feature anyway (we just time out rather than
      do any threaded discovery as suggested by the CRS specs), we're better
      off just not enabling it.
      
      This should fix a slew of problem reports with random devices (generally
      graphics adapters or fairly high-performance networking cards, since it
      only affected PCI-E) not getting properly recognized on these AMD systems.
      
      If we really want to use CRS-SV, we may end up eventually needing a
      whitelist of systems where this should be enabled, along with some kind
      of "pcibios_enable_crs()" query to call the system-specific code.
      Suggested-by: NLoic Prylli <loic@myri.com>
      Tested-by: NKai Ruhnau <kai@tragetaschen.dyndns.org>
      Cc: Matthew Wilcox <matthew@wil.cx>
      Cc: Greg Kroah-Hartman <greg@kroah.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      ad7edfe0
  10. 18 12月, 2007 1 次提交
  11. 10 12月, 2007 1 次提交
  12. 22 10月, 2007 1 次提交
    • K
      Intel IOMMU: PCI generic helper function · 994a65e2
      Keshavamurthy, Anil S 提交于
      When devices are under a p2p bridge, upstream transactions get replaced by the
      device id of the bridge as it owns the PCIE transaction.  Hence its necessary
      to setup translations on behalf of the bridge as well.  Due to this limitation
      all devices under a p2p share the same domain in a DMAR.
      
      We just cache the type of device, if its a native PCIe device
      or not for later use.
      
      [akpm@linux-foundation.org: BUG_ON -> WARN_ON+recover]
      Signed-off-by: NAnil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Muli Ben-Yehuda <muli@il.ibm.com>
      Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
      Cc: Arjan van de Ven <arjan@infradead.org>
      Cc: Ashok Raj <ashok.raj@intel.com>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: Christoph Lameter <clameter@sgi.com>
      Cc: Greg KH <greg@kroah.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      994a65e2
  13. 13 10月, 2007 4 次提交
    • G
      PCI: modify PCI bridge control ISA flag for clarity · 11949255
      Gary Hade 提交于
      Modify PCI Bridge Control ISA flag for clarity
      
      This patch changes PCI_BRIDGE_CTL_NO_ISA to PCI_BRIDGE_CTL_ISA
      and modifies it's clarifying comment and locations where used.
      The change reduces the chance of future confusion since it makes
      the set/unset meaning of the bit the same in both the bridge
      control register and bridge_ctl field of the pci_bus struct.
      Signed-off-by: NGary Hade <garyhade@us.ibm.com>
      Acked-by: NLinas Vepstas <linas@austin.ibm.com>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      11949255
    • G
      PCI: avoid P2P prefetch window for expansion ROMs · fd64cb46
      Gary Hade 提交于
      Avoid creating P2P prefetch window for expansion ROMs
      
      Because of the future possibility that P2P prefetch windows will contain
      address ranges above 4GB some BIOSes are providing space in the P2P
      non-prefetch windows for expansion ROMs.  This is due to expansion ROM
      BAR 32-bit limitation.  When expansion ROM BARs without BIOS assigned
      address(es) are currently found behind a P2P bridge, the kernel attempts
      to create a P2P prefetch window for them even though space for them has
      already been provided in the non-prefetch window.  _CRS on some systems
      with certain resource conservation conscious BIOSes may not provide the
      extra 1MB or more memory resource needed for the expansion ROM motivated
      prefetch window causing resource allocation errors.
      
      This change corrects the problem by removing IORESOURCE_PREFETCH from
      the expansion ROM flags initialization.  It also removes
      IORESOURCE_CACHEABLE which seems inappropriate if only non-cacheable
      memory is available.
      Signed-off-by: NGary Hade <gary.hade@us.ibm.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      fd64cb46
    • G
      PCI: skip ISA ioresource alignment on some systems · 036fff4c
      Gary Hade 提交于
      Skip ISA ioresource alignment on some systems
      
      To conserve limited PCI i/o resource on some IBM multi-node systems, the
      BIOS allocates (via _CRS) and expects the kernel to use addresses in
      ranges currently excluded by pcibios_align_resource() [i386/pci/i386.c].
      This change allows the kernel to use the currently excluded address
      ranges on the IBM x3800, x3850, and x3950.
      Signed-off-by: NGary Hade <gary.hade@us.ibm.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      036fff4c
    • Y
      PCI: fix IDE legacy mode resources · fd6e7321
      Yoichi Yuasa 提交于
      I got the following error on MIPS Cobalt.
      
      PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1
      pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16)
      PCI: Unable to reserve I/O region #3:8@f0000170 for device 0000:00:09.1
      pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16)
      pata_via 0000:00:09.1: no available native port
      
      The legacy mode IDE resources set the following order.
      
      pci_setup_device()
          Legacy mode ATA controllers have fixed addresses.
          IDE resources: 0x1F0-0x1F7, 0x3F6, 0x170-0x177, 0x376
          |
          V
      pcibios_fixup_bus()
          MIPS Cobalt PCI bus regions have the -0x10000000 offset from PCI resources.
          pcibios_fixup_bus() fix PCI bus regions.
          0x1F0 - 0x10000000 = 0xF00001F0
          |
          V
      ata_pci_init_one()
          PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1
      
      In some architectures, PCI bus regions have the offset from PCI resources. 
      For this reason, pci_setup_device() should set PCI bus regions to
      dev->resource[].
      
      [akpm@linux-foundation.org: use struct initialiser]
      Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Cc: Greg KH <greg@kroah.com>
      Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      fd6e7321
  14. 11 9月, 2007 1 次提交
    • R
      PCI: remove devinit from pci_read_bridge_bases · e365c3e7
      Ralf Baechle 提交于
      On MIPS with PCI && !HOTPLUG, I'm currently getting the following modpost
      warning:
      
        MODPOST vmlinux.o
      WARNING: vmlinux.o(.text+0x1ce128): Section mismatch: reference to .init.text:pci_read_bridge_bases (between 'pcibios_fixup_bus' and 'pcibios_enable_device')
      
      On MIPS I have the call chains pci_scan_child_bus -> pcibios_fixup_bus ->
      pci_read_bridge_bases.  pci_scan_child_bus can't be __devinit because it
      it is an exported symbol, thus pcibios_fixup_bus and pci_read_bridge_bases
      can't be either.
      
      For some reason I don't see this issue on x86; I blame compiler differences.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      e365c3e7
  15. 23 8月, 2007 1 次提交
    • B
      PCI: lets kill the 'PCI hidden behind bridge' message · d55bef51
      Bernhard Kaindl 提交于
      Adrian Bunk wrote:
      > Alois Nešpor wrote
      >> PCI: Bus #0b (-#0e) is hidden behind transparent bridge #0a (-#0b) (try 'pci=assign-busses')
      >> Please report the result to linux-kernel to fix this permanently"
      >>
      >> dmesg:
      >> "Yenta: Raising subordinate bus# of parent bus (#0a) from #0b to #0e"
      >> without pci=assign-busses and nothing with pci=assign-busses.
      > 
      > Bernhard?
      
      Ok, lets kill the message. As Alois Nešpor also saw, that's fixed up by Yenta,
      so PCI does not have to warn about it. PCI could still warn about it if
      is_cardbus is 0 in that instance of pci_scan_bridge(), but so far I have
      not seen a report where this would have been the case so I think we can
      spare the kernel of that check (removes ~300 lines of asm) unless debugging
      is done.
      
      History: The whole check was added in the days before we had the fixup
      for this in Yenta and pci=assign-busses was the only way to get CardBus
      cards detected on many (not all) of the machines which give this warning.
      
      In theory, there could be cases when this warning would be triggered and
      it's not cardbus, then the warning should still apply, but I think this
      should only be the case when working on a completely broken PCI setup,
      but one may have already enabled the debug code in drivers/pci and the
      patched check would then trigger.
      
      I do not sign this off yet because it's completely untested so far, but
      everyone is free to test it (with the #ifdef DEBUG replaced by #if 1 and
      pr_debug( changed to printk(.
      
      We may also dump the whole check (remove everything within the #ifdef from
      the source) if that's perferred.
      
      On Alois Nešpor's machine this would then (only when debugging) this message:
      
      "PCI: Bus #0b (-#0e) is partially hidden behind transparent bridge #0a (-#0b)"
      
      "partially" should be in the message on his machine because #0b of #0b-#0e 
      is reachable behind #0a-#0b, but not #0c-#0e.
      
      But that differentiation is now moot anyway because the fixup in Yenta takes
      care of it as far as I could see so far, which means that unless somebody
      is debugging a totally broken PCI setup, this message is not needed anymore,
      not even for debugging PCI.
      
      
      Ok, here the patch with the following changes:
      
      * Refined to say that the bus is only partially hidden when the parent
        bus numbers are not totally way off (outside of) the child bus range
      * remove the reference to pci=assign-busses and the plea to report it
      
      We could add a pure source code-only comment to keep a reference to
      pci=assign-busses the in case when this is triggered by someone who
      is debugging the cause of this message and looking the way to solve it.
      
      From: Bernhard Kaindl <bk@suse.de>
      Cc: stable <stable@kernel.org>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      d55bef51
  16. 17 7月, 2007 1 次提交
  17. 12 7月, 2007 3 次提交