1. 22 1月, 2009 1 次提交
  2. 15 1月, 2009 1 次提交
  3. 07 1月, 2009 1 次提交
    • S
      Resurrect IT8172 IDE controller driver · 391ad190
      Shane McDonald 提交于
      Support for the IT8172 IDE controller was removed from the kernel
      sometime after 2.6.18.  Support for the only boards that used the IT8172
      was removed from the kernel after 2.6.18, as they had never compiled
      since 2.6.0.  However, there are a couple of platforms that use this
      chip: the PMC-Sierra Xiao Hu thin-client computer, which is no longer
      in production, and the Linksys NSS4000 Network Attached Storage box,
      which is based on the Xiao Hu board.  I am attempting to add support
      for the Xiao Hu to the kernel, and this IT8172 IDE controller is the
      first bit of code in this effort.
      
      This patch resurrects the IT8172 IDE controller code.  I began with
      the 2.6.18 version of the it8172.c file, and have moved it forward so
      that it works with the latest version of the kernel.  I have run this
      driver on a PMC-Sierra Xiao Hu board with the 2.6.28 kernel, and
      I have had no problems with it in my configuration.  The attached patch
      applies cleanly against 2.6.28.
      Signed-off-by: NShane McDonald <mcdonald.shane@gmail.com>
      Acked-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
      Cc: alan@lxorguk.ukuu.org.uk
      [bart: s/HWIF(drive)/drive->hwif/]
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      391ad190
  4. 03 1月, 2009 2 次提交
  5. 24 10月, 2008 1 次提交
  6. 22 10月, 2008 1 次提交
  7. 21 10月, 2008 1 次提交
  8. 17 10月, 2008 1 次提交
  9. 01 10月, 2008 1 次提交
  10. 25 9月, 2008 1 次提交
  11. 18 9月, 2008 2 次提交
  12. 06 9月, 2008 1 次提交
  13. 04 9月, 2008 3 次提交
  14. 16 8月, 2008 1 次提交
  15. 08 8月, 2008 1 次提交
  16. 27 7月, 2008 1 次提交
  17. 26 7月, 2008 2 次提交
    • R
      x86: add PCI IDs for AMD Barcelona PCI devices · 021f8b75
      Robert Richter 提交于
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      Cc: oprofile-list <oprofile-list@lists.sourceforge.net>
      Cc: Barry Kasindorf <barry.kasindorf@amd.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      021f8b75
    • A
      edac: i5100 new intel chipset driver · 8f421c59
      Arthur Jones 提交于
      Preliminary support for the Intel 5100 MCH.  CE and UE errors are reported
      along with the current DIMM label information and other memory parameters.
      
      Reasons why this is preliminary:
      
      1) This chip has 2 independent memory controllers which, for best
         perforance, use interleaved accesses to the DDR2 memory.  This
         architecture does not map very well to the current edac data structures
         which depend on symmetric channel access to the interleaved data.
         Without core changes, the best I could do for now is to map both memory
         controllers to different csrows (first all ranks of controller 0, then
         all ranks of controller 1).  Someone much more familiar with the edac
         core than I will probably need to come up with a more general data
         structure to handle the interleaving and de-interleaving of the two
         memory controllers.
      
      2) I have not yet tackled the de-interleaving of the rank/controller
         address space into the physical address space of the CPU.  There is
         nothing fundamentally missing, it is just ending up to be a lot of
         code, and I'd rather keep it separate for now, esp since it doesn't
         work yet...
      
      3) The code depends on a particular i5100 chip select to DIMM mainboard
         chip select mapping.  This mapping seems obvious to me in order to
         support dual and single ranked memory, but it is not unique and DIMM
         labels could be wrong on other mainboards.  There is no way to query
         this mapping that I know of.
      
      4) The code requires that the i5100 is in 32GB mode.  Only 4 ranks per
         controller, 2 ranks per DIMM are supported.  I do not have hardware
         (nor do I expect to have hardware anytime soon) for the 48GB (6 ranks
         per controller) mode.
      
      5) The serial presence detect code should be broken out into a "real"
         i2c driver so that decode-dimms.pl can work.
      Signed-off-by: NArthur Jones <ajones@riverbed.com>
      Signed-off-by: NDoug Thompson <dougthompson@xmission.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      8f421c59
  18. 25 7月, 2008 1 次提交
  19. 23 7月, 2008 1 次提交
  20. 15 7月, 2008 1 次提交
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  22. 08 7月, 2008 1 次提交
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  27. 25 5月, 2008 2 次提交
  28. 01 5月, 2008 1 次提交
  29. 24 4月, 2008 1 次提交
  30. 11 3月, 2008 1 次提交
  31. 22 2月, 2008 1 次提交
  32. 19 2月, 2008 1 次提交
  33. 07 2月, 2008 1 次提交
  34. 06 2月, 2008 1 次提交