- 16 3月, 2011 2 次提交
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由 Dan Williams 提交于
The isci driver needs to retrieve its preboot OROM image which contains necessary runtime parameters like platform specific sas addresses and phy configuration. There is no ROM BAR associated with this area, instead we will need to scan legacy expansion ROM space. 1/ Promote the probe_roms_32 implementation to x86-64 2/ Add a facility to find and map an adapter rom by pci device (according to PCI Firmware Specification Revision 3.0) Signed-off-by: NDave Jiang <dave.jiang@intel.com> LKML-Reference: <20110308183226.6246.90354.stgit@localhost6.localdomain6> Signed-off-by: NDan Williams <dan.j.williams@intel.com> Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
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由 Daniel Drake 提交于
Make OLPC fully depend on device tree, and use it to identify the OLPC platform details. Some nodes are exposed as platform devices where we plan to use device tree for device probing. Signed-off-by: NDaniel Drake <dsd@laptop.org> Acked-by: NGrant Likely <grant.likely@secretlab.ca> LKML-Reference: <20110313151017.C255F9D401E@zog.reactivated.net> Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
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- 11 3月, 2011 2 次提交
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由 Henrik Kretzschmar 提交于
This patch moves some functions and variables into init sections, makes a function static and removes some lines of cruft. Signed-off-by: NHenrik Kretzschmar <henne@nachtwindheim.de> Acked-by: NCyrill Gorcunov <gorcunov@openvz.org> LKML-Reference: <1299826956-8607-2-git-send-email-henne@nachtwindheim.de> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Henrik Kretzschmar 提交于
The extra tsc_sync.o goal definition is superflous. CONFIG_X86_64_SMP depends on CONFIG_SMP and tsc_sync.o is already in the definition of CONFIG_SMP. Signed-off-by: NHenrik Kretzschmar <henne@nachtwindheim.de> Acked-by: NCyrill Gorcunov <gorcunov@openvz.org> LKML-Reference: <1299826956-8607-1-git-send-email-henne@nachtwindheim.de> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 28 2月, 2011 1 次提交
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Until "x86: dt: Cleanup local apic setup" we read the local apic address from the MSR and ignored the entry in DT. Reflect this change in the documentation. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> LKML-Reference: <1298830419-22681-1-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 25 2月, 2011 1 次提交
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由 Thomas Gleixner 提交于
Up to now we force enable the local apic in the devicetree setup uncoditionally and set smp_found_config unconditionally to 1 when a devicetree blob is available. This breaks, when local apic is disabled in the Kconfig. Make it consistent by initializing device tree explicitely before smp_get_config() so a non lapic configuration could be used as well. To be functional that would require to implement PIT as an interrupt host, but the only user of this code until now is ce4100 which requires apics to be available. So we leave this up to those who need it. Tested-by: NSebastian Siewior <bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 24 2月, 2011 24 次提交
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Both OLPC and CE4100 activate CONFIG_OF. OLPC uses PROMTREE while CE uses FLATTREE. Compiling for OLPC only breaks due to missing flat tree functions and variables. Use proper wrappers and provide an empty x86_flattree_get_config() inline so OF=y FLATTREE=n builds and works. [ tglx: Make it work with HPET_TIMER=n and make a function static ] Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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This allows to load the OF driver based informations from the device tree. Systems without BIOS may need to perform some initialization. PowerPC creates a PNP device from the OF information and performs this kind of initialization in their private PCI quirk. This looks more generic. This patch also avoids registering the platform RTC driver on X86 if we have a device tree blob. Otherwise we would setup the device based on the hardcoded information in arch/x86 rather than the device tree based one. [ tglx: Changed "int of_have_populated_dt()" to bool as recommended by Grant ] Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org Cc: rtc-linux@googlegroups.com Cc: Alessandro Zummo <a.zummo@towertech.it> LKML-Reference: <1298405266-1624-12-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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Use device tree information to setup IO_APIC configuration, interrupt routing, HPET and everything else which cannot be enumerated by other means. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-11-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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ioapic_xlate provides a translation from the information in device tree to ioapic related informations. This includes - obtaining hw irq which is the vector number "=> pin number + gsi" - obtaining type (level/edge/..) - programming this information into ioapic ioapic_add_ofnode adds an irq_domain based on informations from the device tree. This information (irq_domain) is required in order to map a device to its proper interrupt controller. [ tglx: Adapted to the io_apic changes, which let us move that whole code to devicetree.c ] Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-10-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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For now we probe these busses and we change this to board dependent probes once we have to. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-9-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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x86_of_pci_init() does two things: - it provides a generic irq enable and disable function. enable queries the device tree for the interrupt information, calls ->xlate on the irq host and updates the pci->irq information for the device. - it walks through PCI bus(es) in the device tree and adds its children (device) nodes to appropriate pci_dev nodes in kernel. So the dtb node information is available at probe time of the PCI device. Adding a PCI bus based on the information in the device tree is currently not supported. Right now direct access via ioports is used. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Tested-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-8-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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Set hpet_address based on information provied form DTB Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org Cc: Dirk Brandewie <dirk.brandewie@gmail.com> LKML-Reference: <1298405266-1624-7-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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APIC and IO_APIC have to be added to the system early because native_init_IRQ() requires it. In order to obtain the address of the ioapic the device tree has to be unflattened so of_address_to_resource() works. The device tree is relocated to ensure it is always covered by the kernel mapping. That way the boot loader does not have to make any assumptions about kernel's memory layout. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org Cc: Dirk Brandewie <dirk.brandewie@gmail.com> LKML-Reference: <1298405266-1624-6-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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The here introduced irq_domain abstraction represents a generic irq controller. It is a subset of powerpc's irq_host which is going to be renamed to irq_domain and then become generic. This implementation will be removed once it is generic. The xlate callback is resposible to parse irq informations like irq type and number and returns the hardware irq number which is reported by the hardware as active. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Tested-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-5-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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History: v1..v2: - dropped device_type except for cpu & pci. I have the compatible string for pci so I can drop the device_type once it is possible - I lowercased all compatible types. I will need to resend some patches which have upper case intel - The cpu had the same compatible string as the soc node. So I added to the soc node -immr for internel memory mapped registers. - I added generic names for all parts. - I reworked the i2c bars matching the way you suggested. I added a compatible node for the PCI device which only the PCI ids in its compatible string. The bars (each represents a complete i2c controller) have a "intel,ce4100-i2c-controller" compatible node. It is not used by the driver. The driver is probed via PCI ids (by the pci subsystem not OF) and matches the bar address against the ressource in the child node. Once there is a hit the node is attached. - The SPI driver is also probed via pci. However I also attached a compatible property based on PCI ids v2..v3: - intel,ce4100-immr become intel,ce4100-cp. cp stands for core peripherals. The Atom data sheet talks here about ACPI devices. Since we don't have ACPI this does not apply here. - The interrupt map is gone. There are now plenty of device nodes. - The "unit address string" got fixed, it uses not DD,V format. v3..v4: - added descriptions for compatible nodes introduced here: - intel,ce4100-ioapic - intel,ce4100-lapic - intel,ce4100-hpet - intel,ce4100 - intel,ce4100-cp - intel,ce4100-pci - added a description about I2C controller magic. - Added gpio-controller and gpio-cells property to gpio devices. Those properties are not (yet) used. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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This patch adds minimal support for device tree on x86. The device tree blob is passed to the kernel via setup_data which requires at least boot protocol 2.09. Memory size, restricted memory regions, boot arguments are gathered the traditional way so things like cmd_line are just here to let the code compile. The current plan is use the device tree as an extension and to gather information which can not be enumerated and would have to be hardcoded otherwise. This includes things like - which devices are on this I2C/SPI bus? - how are the interrupts wired to IO APIC? - where could my hpet be? Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-3-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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This patch ensures that the memory passed from parse_setup_data() is large enough to cover the complete data structure. That means that the conditional mapping in parse_e820_ext() can go. While here, I also attempt not to map two pages if the address is not aligned to a page boundary. Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com> Cc: sodaville@linutronix.de Cc: devicetree-discuss@lists.ozlabs.org LKML-Reference: <1298405266-1624-2-git-send-email-bigeasy@linutronix.de> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
Reason: Devicetree based ioapic setup depends on the apic changes. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
Required for devicetree based io_apic configuration. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
io_apic_set_pci_routing() and mp_save_irq() check the pin_programmed bit before calling io_apic_setup_irq_pin() and set the bit when the pin was setup. Move that duplicated code into a separate function and use it. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
There is no point to have irq_trigger() and irq_polarity() as wrappers around the MPBIOS_* camel case functions. Get rid of both the inlines and the ugly camel case. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
No users outside of io_apic.c. Mark bad_ioapic() __init while at it. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
Another version of the same thing. Only set the pin programmed, when the setup function succeeds. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
Replace the duplicated code. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
The only difference here is that we did not call __add_pin_to_irq_node() for the legacy irqs, but that's not worth 30 lines of extra code. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
Remove the duplicated code and call the function. It does not matter whether we allocated the cfg before calling setup_local_APIC() and we can set the irq chip and handler after that as well. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
There are about four places in the ioapic code which do exactly the same setup sequence. Also the OF based ioapic setup needs that function to avoid putting the OF specific code into ioapic.c Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
Two consecutive for(...) for(...) lines to avoid an extra indentation are just horrible to read. I had to look more than once to figure out what the code is doing. Split out the inner loop into a separate function. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Thomas Gleixner 提交于
This is debug code and it does not matter at all whether we print each not connected pin in an extra line or try to be extra clever. Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 23 2月, 2011 10 次提交
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由 Thomas Gleixner 提交于
Stupid me missed the functions called from setup.c. Add the stubs back for OLPC=n Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Henrik Kretzschmar 提交于
Since commit 7cd92366 lAPIC enabled accidently the IOAPIC, which now gets fixed. Signed-off-by: NHenrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-5-git-send-email-henne@nachtwindheim.de> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Henrik Kretzschmar 提交于
This patch adds IOAPIC dummy functions for compilation with local APIC, but without IOAPIC. The local variable ioapic_entries in enable_IR_x2apic() does not need initialization anymore, since the dummy returns NULL. Signed-off-by: NHenrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-4-git-send-email-henne@nachtwindheim.de> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Henrik Kretzschmar 提交于
Currently arch_disable_smp_support() on x86 disables only the support for the IOAPIC and is also compiled in if SMP-support is not. Therefore this function is renamed to disable_ioapic_support(), which meets its purpose and is only compiled in the kernel when IOAPIC support is also. A new arch_disable_smp_support() is created in smpboot.c, which calls disable_ioapic_support() and gets only compiled in the kernel when SMP support is also. Signed-off-by: NHenrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-3-git-send-email-henne@nachtwindheim.de> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Henrik Kretzschmar 提交于
This is a dummy function, used when no IOAPIC is compiled in. Signed-off-by: NHenrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-2-git-send-email-henne@nachtwindheim.de> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Henrik Kretzschmar 提交于
This enum is used by non IOAPIC code, so apicdef.h is the best place for it. Signed-off-by: NHenrik Kretzschmar <henne@nachtwindheim.de> LKML-Reference: <1298385487-4708-1-git-send-email-henne@nachtwindheim.de> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Thomas Gleixner 提交于
OLPC_OPENFIRMWARE_DT is just there to be selected by OLPC and selects OF_PROMTREE. So let OLPC select OF_PROMTREE and remove that extra config indirection. Fixup code and Makefile and use CONFIG_OF_PROMTREE instead. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Andres Salomon <dilinger@queued.net>
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由 Thomas Gleixner 提交于
Neither CONFIG_OLPC_OPENFIRMWARE nor CONFIG_OLPC_OPENFIRMWARE_DT are really necessary. OLPC selects OLPC_OPENFIRMWARE unconditionally, so move the "select OF" part under OLPC config option and fixup the dependencies in Makefiles and code. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Andres Salomon <dilinger@queued.net>
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由 Thomas Gleixner 提交于
OLPC selects OLPC_OPENFIRMWARE unconditionally. If OLPC=n then the OLPC_OPENFIRMWARE functionality is pointless. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Andres Salomon <dilinger@queued.net>
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由 Thomas Gleixner 提交于
OLPC is under if X86_32 already. Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Andres Salomon <dilinger@queued.net>
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