The annotation on the addr_map_cfg variable is in the wrong place.

Without this patch, building mv78xx0_defconfig results in:

/home/arnd/linux-arm/arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: initialization from incompatible pointer type [enabled by default]
/home/arnd/linux-arm/arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near initialization for 'addr_map_cfg.win_cfg_base') [enabled by default]
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NAndrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>

The functions for address mapping management now take void __iomem
pointers, so we remove the temporary "unsigned long" casts from the
mach-*/common.c files.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

We now define all virtual base address constants using IOMEM() so that
those are naturally typed as void __iomem pointers, and we do the
necessary adjustements in the mach-mv78xx0 code.

Note that we introduce a few temporary additional "unsigned long"
casts when calling into plat-orion functions. Those are removed by
followup patches converting plat-orion functions to void __iomem
pointers as well.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Patch b6d1c33a "ARM: Orion: Consolidate the address map setup" tried
to merge the address map for the four orion platforms, but apparently
got it wrong for mv78xx0. Admittedly I don't understand what this
code actually does, but it's clear that the current version is
wrong.

Without this patch, building mv78xx0_defconfig results in:

arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: initialization from incompatible pointer type [enabled by default]
arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near initialization for 'addr_map_cfg.win_cfg_base') [enabled by default]
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NAndrew Lunn <andrew@lunn.ch>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolas Pitre <nico@linaro.org>

Move mv78xx0 PCI to fixed i/o mapping and remove io.h. This changes the PCI
bus addresses from the cpu address to 0 based. It appears that there is
translation h/w for this, but its untested.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>

Move the *_mbus_dram_info structure into the orion platform and call it
orion_mbus_dram_info everywhere.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NMichael Walle <michael@walle.cc>
Acked-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Compile tested on Dove, orion5x, mv78xx0. Boot tested on Kirkwood.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NMichael Walle <michael@walle.cc>
Acked-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.

This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.
Signed-off-by: NStanislav Samsonov <samsonov@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>

The Marvell Kirkwood (88F6000) is a family of ARM SoCs based on a
Shiva CPU core, and features a DDR2 controller, a x1 PCIe interface,
a USB 2.0 interface, a SPI controller, a crypto accelerator, a TS
interface, and IDMA/XOR engines, and depending on the model, also
features one or two Gigabit Ethernet interfaces, two SATA II
interfaces, one or two TWSI interfaces, one or two UARTs, a
TDM/SLIC interface, a NAND controller, an I2S/SPDIF interface, and
an SDIO interface.

This patch adds supports for the Marvell DB-88F6281-BP Development
Board and the RD-88F6192-NAS and the RD-88F6281 Reference Designs,
enabling support for the PCIe interface, the USB interface, the
ethernet interfaces, the SATA interfaces, the TWSI interfaces, the
UARTs, and the NAND controller.
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>