- 15 12月, 2016 1 次提交
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由 Varun Prakash 提交于
T6 adapters reduce number of completions to host by generating single completion for all the directly placed(DDP) iSCSI pdus in a sequence. This patch adds new structure for completion hw cmd (struct cpl_rx_iscsi_cmp) and implements T6 completion feature. Signed-off-by: NVarun Prakash <varun@chelsio.com> Signed-off-by: NMartin K. Petersen <martin.petersen@oracle.com>
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- 19 8月, 2016 1 次提交
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由 Hariprasad Shenai 提交于
Signed-off-by: NAtul Gupta <atul.gupta@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 6月, 2016 1 次提交
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由 Hariprasad S 提交于
Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDoug Ledford <dledford@redhat.com>
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- 14 5月, 2016 1 次提交
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由 Hariprasad S 提交于
The FID value in a ULP_MEMIO command needs to be set to an IQ ID of a queue configured for our PF. The FID/IQ id is used to index into the PCIE FID table, to find out on which function the DMA needs to be issued. Essentially, every DMA needs to have the ingress queue. The exact ingress queue doesn't matter, but it needs to be an ingress queue associated with the function you want to see the DMA on. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDoug Ledford <dledford@redhat.com>
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- 22 3月, 2016 5 次提交
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由 Varun Prakash 提交于
move delayed ack macro definitions to common header file t4_msg.h. Signed-off-by: NVarun Prakash <varun@chelsio.com> Acked-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NNicholas Bellinger <nab@linux-iscsi.org>
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由 Varun Prakash 提交于
add structure, macro and constant definitions for iSCSI Tx and Rx. Signed-off-by: NVarun Prakash <varun@chelsio.com> Acked-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NNicholas Bellinger <nab@linux-iscsi.org>
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由 Varun Prakash 提交于
move struct cpl_rx_data_ddp definition to common header file t4_msg.h. Signed-off-by: NVarun Prakash <varun@chelsio.com> Acked-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NNicholas Bellinger <nab@linux-iscsi.org>
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由 Varun Prakash 提交于
move struct ulptx_idata definition to common header file t4_msg.h. Signed-off-by: NVarun Prakash <varun@chelsio.com> Acked-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NNicholas Bellinger <nab@linux-iscsi.org>
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由 Varun Prakash 提交于
move struct tcp_options, struct cpl_pass_accept_req, enum defining congestion control algorithms and associated macros to common header file t4_msg.h Signed-off-by: NVarun Prakash <varun@chelsio.com> Acked-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NNicholas Bellinger <nab@linux-iscsi.org>
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- 01 3月, 2016 1 次提交
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由 Hariprasad S 提交于
This series provides support for iWARP applications to specify a TOS value and have that map to a VLAN Priority for iw_cxgb4 iWARP connections. In iw_cxgb4, when allocating an L2T entry, pass the skb_priority based on the tos value in the cm_id. Also pass the correct tos value during connection setup so the passive side gets the client's desired tos. When sending the FLOWC work request to FW, if the egress device is in a vlan, then use the vlan priority bits as the scheduling class. This allows associating RDMA connections with scheduling classes to provide traffic shaping per flow. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDoug Ledford <dledford@redhat.com>
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- 11 2月, 2016 1 次提交
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由 Hariprasad Shenai 提交于
This series provides support for iWARP applications to specify a TOS value and have that map to a VLAN Priority for iw_cxgb4 iWARP connections. In iw_cxgb4, when allocating an L2T entry, pass the skb_priority based on the tos value in the cm_id. Also pass the correct tos value during connection setup so the passive side gets the client's desired tos. When sending the FLOWC work request to FW, if the egress device is in a vlan, then use the vlan priority bits as the scheduling class. This allows associating RDMA connections with scheduling classes to provide traffic shaping per flow. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 10月, 2015 1 次提交
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由 Hariprasad S 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDoug Ledford <dledford@redhat.com>
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- 21 7月, 2015 1 次提交
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由 Anish Bhatt 提交于
Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 02 6月, 2015 1 次提交
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由 Hariprasad Shenai 提交于
Adds NIC driver related changes for T6 adapter. Register related changes, MC related changes, VF related changes, doorbell related changes, debugfs changes, etc Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 5月, 2015 1 次提交
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由 Hariprasad Shenai 提交于
Cleanup few MACROS left out in t4_hw.h to be consistent with the existing ones. Also replace few hardcoded values with MACROS. Also update comments for some code Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 25 3月, 2015 1 次提交
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由 Varun Prakash 提交于
This patch adds new header file cxgb4_fcoe.h and defines new macros for FCoE support in cxgb4 driver. Signed-off-by: NVarun Prakash <varun@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 1月, 2015 2 次提交
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由 Hariprasad Shenai 提交于
iw_cxgb4/cxgb4/cxgb4vf/cxgb4i/csiostor: Cleanup register defines/macros related to all other cpl messages This patch cleanups all other macros/register define related to CPL messages that are defined in t4_msg.h and the affected files Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
This patch cleanups all macros/register define related to connection management CPL messages that are defined in t4_msg.h and the affected files Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 11月, 2014 1 次提交
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由 Anish Bhatt 提交于
Refactored all macros used in cxgb4i as part of previously started cxgb4 macro names cleanup. Makes them more uniform and avoids namespace collision. Minor changes in other drivers where required as some of these macros are used by multiple drivers, affected drivers are iw_cxgb4, cxgb4(vf) & csiostor Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 10月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Update the lso length for T5 adapter and fix PIDX_T5 macro Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 06 8月, 2014 1 次提交
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由 Anish Bhatt 提交于
These belong to the t4 msg header, will ensure there is no accidental code duplication in the future Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 18 7月, 2014 2 次提交
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由 Anish Bhatt 提交于
Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Anish Bhatt 提交于
This define is used by cxgb4i and iw_cxgb4, moving to avoid code duplication Signed-off-by: NAnish Bhatt <anish@chelsio.com> Acked-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 6月, 2014 1 次提交
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由 Anish Bhatt 提交于
Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 6月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
Fixed a bug that shows up with recv window sizes that exceed the size of the RCV_BUFSIZ field in opt0 (>= 1024K). If the recv window exceeds this, then we specify the max possible in opt0, add add the rest in via a RX_DATA_ACK credits. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Select the appropriate hw mtu index and initial sequence number to optimize hw memory performance. Add new cxgb4_best_aligned_mtu() which allows callers to provide enough information to be used to [possibly] select an MTU which will result in the TCP Data Segment Size (AKA Maximum Segment Size) to be an aligned value. If an RTR message exhange is required, then align the ISS to 8B - 1 + 4, so that after the SYN the send seqno will align on a 4B boundary. The RTR message exchange will leave the send seqno aligned on an 8B boundary. If an RTR is not required, then align the ISS to 8B - 1. The goal is to have the send seqno be 8B aligned when we send the first FPDU. Based on original work by Casey Leedom <leeedom@chelsio.com> and Steve Wise <swise@opengridcomputing.com> Signed-off-by: NCasey Leedom <leedom@chelsio.com> Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 3月, 2014 1 次提交
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由 Steve Wise 提交于
Based on original work by Anand Priyadarshee <anandp@chelsio.com>. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 8月, 2013 1 次提交
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由 Vipul Pandya 提交于
Add cxgb4_create_server6 and cxgb4_remove_server routines to create and remove listening IPv6 servers. Return success (0) from cxgb4_create_server in case of ctrl queue congestion since in case of congestion, passive open request gets queued and gets processed later. If a non-zero value were returned it would be treated as an error and the ULD would free STID, which can result in an error in passive open reply. Add cpl structure for active open request with IPv6 address for T5. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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- 30 4月, 2013 2 次提交
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由 Vipul Pandya 提交于
Newer firmware can post CPL_SGE_EGR_UPDATE message encapsulated in a CPL_FW4_MSG as follows flit0 rss_header (if DropRSS == 0 in IQ context) flit1 CPL_FW4_MSG cpl flit2 rss_header w/opcode CPL_SGE_EGR_UPDATE flit3 CPL_SGE_EGR_UPDATE cpl So FW4_MSG CPLs with a newly created type of FW_TYPE_RSSCPL have the CPL_SGE_EGR_UPDATE CPL message in flit 2 of the FW4_MSG. Firmware can still post regular CPL_SGE_EGR_UPDATE messages, so the drivers need to handle both. This patch also writes a new parameter to firmware requesting encapsulated EGR_UPDATE. This allows firmware with this support to not break older drivers. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Vipul Pandya 提交于
Newer firmware can post CPL_SGE_EGR_UPDATE message encapsulated in a CPL_FW4_MSG as follows flit0 rss_header (if DropRSS == 0 in IQ context) flit1 CPL_FW4_MSG cpl flit2 rss_header w/opcode CPL_SGE_EGR_UPDATE flit3 CPL_SGE_EGR_UPDATE cpl So FW4_MSG CPLs with a newly created type of FW_TYPE_RSSCPL have the CPL_SGE_EGR_UPDATE CPL message in flit 2 of the FW4_MSG. Firmware can still post regular CPL_SGE_EGR_UPDATE messages, so the drivers need to handle both. This patch also writes a new parameter to firmware requesting encapsulated EGR_UPDATE. This allows firmware with this support to not break older drivers. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 3月, 2013 2 次提交
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由 Vipul Pandya 提交于
It enables direct DMA by HW to memory region PBL arrays and fast register PBL arrays from host memory, vs the T4 way of passing these arrays in the WR itself. The result is lower latency for memory registration, and larger PBL array support for fast register operations. This patch also updates ULP_TX_MEM_WRITE command fields for T5. Ordering bit of ULP_TX_MEM_WRITE is at bit position 22 in T5 and at 23 in T4. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Santosh Rastapur 提交于
Signed-off-by: NSantosh Rastapur <santosh@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 20 12月, 2012 3 次提交
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由 Vipul Pandya 提交于
It establishes passive open connection through firmware work request. Passive open connection will go through this path as now instead of listening server we create a server filter which will redirect the incoming SYN packet to the offload queue. After this driver tries to establish the connection using firmware work request. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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由 Vipul Pandya 提交于
It enables establishing active open connection using fw_ofld_connection work request when cpl_act_open_rpl says TCAM full error which may be because of LE hash collision. Current support is only for IPv4 active open connections. Sets ntuple bits in active open requests. For T4 firmware greater than 1.4.10.0 ntuple bits are required to be set. Adds nocong and enable_ecn module parameter options. Signed-off-by: NVipul Pandya <vipul@chelsio.com> [ Move all FW return values to t4fw_api.h. - Roland ] Signed-off-by: NRoland Dreier <roland@purestorage.com>
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由 Vipul Pandya 提交于
The T4 architecture is capable of filtering ingress packets at line rate using the rule in TCAM. If packet hits a rule in the TCAM then it can be either dropped or passed to the receive queues based on a rule settings. This patch adds framework for managing filters and to use T4's filter capabilities. It constructs a Firmware Filter Work Request which writes the filter at a specified index to get the work done. It hosts shadow copy of ingress filter entry to check field size limitations and save memory in the case where the filter table is large. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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- 27 11月, 2012 1 次提交
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由 Naresh Kumar Inna 提交于
This patch contains updates to firmware/hardware header files shared between csiostor and cxgb4/cxgb4vf, and the resulting changes to the cxgb4/cxgb4vf source files. Signed-off-by: NNaresh Kumar Inna <naresh@chelsio.com> Cc: David Miller <davem@davemloft.net> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 11 8月, 2011 1 次提交
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由 Jeff Kirsher 提交于
Moves the drivers for the Chelsio chipsets into drivers/net/ethernet/chelsio/ and the necessary Kconfig and Makefile changes. CC: Divy Le Ray <divy@chelsio.com> CC: Dimitris Michailidis <dm@chelsio.com> CC: Casey Leedom <leedom@chelsio.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 15 3月, 2011 1 次提交
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由 Steve Wise 提交于
Set the ULP mode for initial RDMA connection setup to the proper DDP mode. This avoids wasting some HW resources while in streaming mode. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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- 03 8月, 2010 1 次提交
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由 Dimitris Michailidis 提交于
The checksum provided by the device doesn't include the L3 headers, as IPv6 expects. Signed-off-by: NDimitris Michailidis <dm@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 6月, 2010 1 次提交
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由 Casey Leedom 提交于
Split cpl_tx_pkt_lso into core message structure and encapsulated message, make RSPD_LEN macro match other response descriptor macros. Signed-off-by: Casey Leedom Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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