1. 23 3月, 2013 2 次提交
  2. 01 3月, 2013 28 次提交
  3. 23 2月, 2013 1 次提交
  4. 14 2月, 2013 1 次提交
  5. 26 1月, 2013 1 次提交
  6. 18 1月, 2013 1 次提交
  7. 02 1月, 2013 4 次提交
  8. 20 12月, 2012 2 次提交
    • J
      watchdog: Orion: Fix possible null-deference in orion_wdt_probe · 8c4c419c
      Jason Gunthorpe 提交于
      If the DT does not include a regs parameter then the null res
      would be dereferenced.
      Signed-off-by: NJason Gunthorpe <jgunthorpe@obsidianresearch.com>
      Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      8c4c419c
    • T
      watchdog: sp5100_tco: Add SB8x0 chipset support · 740fbddf
      Takahisa Tanaka 提交于
      The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
      support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
      offset address for watchdog timer was changed from SB8x0 chipset.
      
      The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
      AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
      Register Reference Guide (Page 166).
      
        WatchDogTimerControl 69h
        WatchDogTimerBase0   6Ch
        WatchDogTimerBase1   6Dh
        WatchDogTimerBase2   6Eh
        WatchDogTimerBase3   6Fh
      
      In contrast, the offset address of SB8x0 chipset is as follows, quote from
      AMD SB800-Series Southbridges Register Reference Guide (Page 147).
      
        WatchDogTimerEn      48h
        WatchDogTimerConfig  4Ch
      
      So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
      address (for example, 0xbafe00) from wrong offset address, and the following
      message is logged.
      
         SP5100 TCO timer: mmio address 0xbafe00 already in use
      
      With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
      iomem resource conflict. The processing of this patch is as follows.
      
       Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
               and 0xCD7).
        - Go to the step 7 if obtained address hasn't conflicted with other
          resource. But, currently, the address (0xfec000f0) conflicts with the
          IOAPIC MMIO address, and the following message is logged.
      
             SP5100 TCO timer: mmio address 0xfec000f0 already in use
      
          0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
          next step.
      
       Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
               SB8x0,  PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
               register.
        - Go to the step 7 if these register has enabled by BIOS, and obtained
          address hasn't conflicted with other resource.
        - If above condition isn't true, go to the next step.
      
       Step 3) Attempt to get the free MMIO address from allocate_resource().
        - Go to the step 7 if these register has enabled by BIOS, and obtained
          address hasn't conflicted with other resource.
        - Driver initialization has failed if obtained address has conflicted
          with other resource, and no 'force_addr' parameter is specified.
      
       Step 4) Use the specified address If 'force_addr' parameter is specified.
        - allocate_resource() function may fail, when the PCI bridge device occupies
          iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
          I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
          parameter, sp5100_tco driver directly can assign MMIO address for watchdog
          timer from free iomem region. Note that It's dangerous to specify wrong
          address in the 'force_addr' parameter.
      
            Example of force_addr parameter use
              # cat /proc/iomem
              ...snip...
              fec00000-fec003ff : IOAPIC 0
                                            <--- free MMIO region
              fec10000-fec1001f : pnp 00:0b
              fec20000-fec203ff : IOAPIC 1
              ...snip...
              # cat /etc/modprobe.d/sp5100_tco.conf
              options sp5100_tco force_addr=0xfec00800
              # modprobe sp5100_tco
              # cat /proc/iomem
              ...snip...
              fec00000-fec003ff : IOAPIC 0
              fec00800-fec00807 : SP5100 TCO  <--- watchdog timer MMIO address
              fec10000-fec1001f : pnp 00:0b
              fec20000-fec203ff : IOAPIC 1
              ...snip...
              #
      
        - Driver initialization has failed if specified address has conflicted
          with other resource.
      
       Step 5) Disable the watchdog timer
        - To rewrite the watchdog timer register of the chipset, absolutely
          guarantee that the watchdog timer is disabled.
      
       Step 6) Re-program the watchdog timer MMIO address to chipset.
        - Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
          indirect I/O (0xCD6 and 0xCD7).
      
       Step 7) Enable and setup the watchdog timer
      
      This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
      DL165G7). therefore I believe that it's no problem to re-program the MMIO
      address for watchdog timer to chipset during disabled watchdog. However,
      I'm not sure about it, because I don't know much about chipset programming.
      
      So, any comments will be welcome.
      
      Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176Tested-by: NArkadiusz Miskiewicz <arekm@maven.pl>
      Tested-by: NPaul Menzel <paulepanter@users.sourceforge.net>
      Signed-off-by: NTakahisa Tanaka <mc74hc00@gmail.com>
      Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
      740fbddf