- 30 4月, 2013 1 次提交
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由 Kevin Hao 提交于
The reg property in the pci bridge device node is used to bind this device node to the pci bridge device. Then all the pci devices under this bridge could use the interrupt maps defined in this device node to do the irq translation. So if this property is missed, the pci traditional irq mechanism will not work. Signed-off-by: NKevin Hao <haokexin@gmail.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 11 4月, 2013 2 次提交
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由 Vakul Garg 提交于
The crypto node now contains a new property 'fsl,sec-era'. This is required so that applications can retrieve era info without having to be able to read SEC's register space. Signed-off-by: NVakul Garg <vakul@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Vakul Garg 提交于
Removing qoriq-sec4.1-0.dtsi as it is not used by any soc anymore. Signed-off-by: NVakul Garg <vakul@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 4月, 2013 1 次提交
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由 Shaveta Leekha 提交于
B4860 and B4420 are similar that share some commonalities * common features have been added in b4si-pre.dtsi and b4si-post.dtsi * differences are added in respective silicon files of B4860 and B4420 There are several things missing from the device trees of B4860 and B4420: * DPAA related nodes (Qman, Bman, Fman, Rman) * DSP related nodes/information * serdes, sfp(security fuse processor), thermal, gpio, maple, cpri, quad timers nodes Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NVakul Garg <vakul@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 09 4月, 2013 1 次提交
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由 Kumar Gala 提交于
* Fix cpu unit address to match reg * Update compatible for rcpm & clockgen to be 2.0 instead of 2 Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 04 4月, 2013 1 次提交
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由 Shaveta Leekha 提交于
Signed-off-by: NVakul Garg <vakul@freescale.com> Signed-off-by: NShaveta Leekha <shaveta@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 19 3月, 2013 3 次提交
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由 Kumar Gala 提交于
As the T4240 is based on corenet chassis v2.0 spec we update the global utilities (GUTS) device config compatiable to reflect this. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Stephen George 提交于
Identifies the epu as compatible with Chassis v1 Debug IP. Signed-off-by: NStephen George <Stephen.George@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Stephen George 提交于
Signed-off-by: NStephen George <Stephen.George@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 13 3月, 2013 2 次提交
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由 Ramneek Mehresh 提交于
Add first usb controller node for qonverge qoriq platforms like B4860, etc Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kumar Gala 提交于
Enable a baseline T4240 SoC to boot. There are several things missing from the device trees for T4240: * Proper PAMU topology information * DPAA related nodes (Qman, Bman, Fman, Rman, DCE) * Prefetch Manager * Thermal monitor unit * Interlaken Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NVakul Garg <vakul@freescale.com> Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NLaurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 06 3月, 2013 3 次提交
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由 Vakul Garg 提交于
Add device tree for SEC (crypto engine) version 5.0 used on T4240. Signed-off-by: NVakul Garg <vakul@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Stuart Yoder 提交于
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Stuart Yoder 提交于
-also define a binding for fsl,eref-* properties Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 13 2月, 2013 3 次提交
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由 Po Liu 提交于
This facilitates getting the physical address of the SEC node. Signed-off-by: NLiu po <po.liu@freescale.com> Reviewed-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
Fix and/or improve the compatible strings of the PCI device tree nodes for some Freescale SOCs. This fixes some issues and improves consistency among the SOCs. Specifically: 1) The P1022 has a v1 PCIe controller, so the compatible property should just say "fsl,mpc8548-pcie". U-Boot does not look for "fsl,p1022-pcie", so it wasn't fixing up the node. 2) The P4080 has a v2.1 PCIe controller, so add that version-specific string to the device tree. Update the kernel to also look for that string. Currently, the kernel looks for "fsl,p4080-pcie" specifically, but eventually that check should be deleted. 3) The P1010 device tree claims compatibility with v2.2 and v2.3, but that's redundant. No other device tree does this. Remove the v2.2 string. 4) The kernel looks for both "fsl,p1023-pcie" and "fsl,qoriq-pcie-v2.2", even though the P1023 device trees has always included both strings. Remove the search for "fsl,p1023-pcie". Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
The PAMU caches use the LIODNs to determine which cache lines hold the entries for the corresponding LIODs. The LIODNs must therefore be carefully assigned to avoid cache thrashing -- two active LIODs with LIODNs that put them in the same cache line. Currently, LIODNs are statically assigned by U-Boot, but this has limitations. LIODNs are assigned even for devices that may be disabled or unused by the kernel. Static assignments also do not allow for device drivers which may know which LIODs can be used simultaneously. In other words, we really should assign LIODNs dynamically in Linux. To do that, we need to describe the PAMU device and cache topologies in the device trees. Signed-off-by: NTimur Tabi <timur@freescale.com> Acked-by: NStuart Yoder <stuart.yoder@freescale.com> Acked-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 25 11月, 2012 1 次提交
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由 Xuelin Shi 提交于
The RaidEngine is a new Freescale hardware that used for parity computation offloading in RAID5/6. This patch adds the device node in device tree and related binding documentation. Signed-off-by: NHarninder Rai <harninder.rai@freescale.com> Signed-off-by: NNaveen Burmi <naveenburmi@freescale.com> Signed-off-by: NXuelin Shi <b29237@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 13 9月, 2012 4 次提交
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由 Olivia Yin 提交于
power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. This patch update all the e5500 platforms. Signed-off-by: NLiu Yu <yu.liu@freescale.com> Signed-off-by: NOlivia Yin <hong-hua.yin@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Olivia Yin 提交于
power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. The patch update all the e500mc platforms. Signed-off-by: NLiu Yu <yu.liu@freescale.com> Signed-off-by: NOlivia Yin <hong-hua.yin@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Olivia Yin 提交于
power-isa-version and power-isa-* are cpu node general properties defined in ePAPR. If the power-isa-version property exists, then for each category from the Categories section of Book I of the Power ISA version indicated, the existence of a property named power-isa-[CAT], where [CAT] is the abbreviated category name with all uppercase letters converted to lowercase, indicates that the category is supported by the implementation. The patch update all e500v2 platforms. Signed-off-by: NLiu Yu <yu.liu@freescale.com> Signed-off-by: NOlivia Yin <hong-hua.yin@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kim Phillips 提交于
Add device tree (dtsi) files for the Freescale P5040 SOC. Since this SOC introduces SEC v5.2, add the dtsi file for that also. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 8月, 2012 1 次提交
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由 Shengzhou Liu 提交于
Add the missing usb controller version info and port0, which is required during setup usb phy. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 10 7月, 2012 3 次提交
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由 Zhicheng Fan 提交于
Add device tree nodes to enable ucc uart support on P1025RDB. Signed-off-by: NZhicheng Fan <B32736@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Prabhakar Kushwaha 提交于
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. The BSC9131 is integrated SoC that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. BSC9131RDB Overview ---------------------- BSC9131 SoC 1Gbyte DDR3 (on board DDR) 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory USB-ULPI eTSEC1: Connected to RGMII PHY eTSEC2: Connected to RGMII PHY DUART interface: supports one UARTs up to 115200 bps for console display Linux runs on e500v2 core and access some DSP peripherals like AIC Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NAkhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NRajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
This reverts commit 96cc017c. The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 20 4月, 2012 1 次提交
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由 Mingkai Hu 提交于
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 17 3月, 2012 4 次提交
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由 Diana CRACIUN 提交于
The MSIIR register for each MSI bank is aliased to a different address. The MSI node reg property was updated to contain this address: e.g. reg = <0x41600 0x200 0x44140 4>; The first region contains the address and length of the MSI register set and the second region contains the address of the aliased MSIIR register at 0x44140. Signed-off-by: NDiana CRACIUN <Diana.Craciun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Zhao Chenhui 提交于
Correct ethernet1 and add ethernet2 and ethernet3. Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 chenhui zhao 提交于
Enable RapidIO and add rapidio and rmu nodes to dts. Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Liu Shuo 提交于
Fix the compatible string of sec 4.0 to match with CAAM driver according to Documentation/devicetree/bindings/crypto/fsl-sec4.txt Signed-off-by: NLiu Shuo <shuo.liu@freescale.com> Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 16 3月, 2012 4 次提交
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由 Timur Tabi 提交于
The Freescale P1022 has a unique pin muxing "feature" where the DIU video controller's video signals are muxed with 24 of the local bus address signals. When the DIU is enabled, the bulk of the local bus is disabled, preventing access to memory-mapped devices like NOR flash and the pixis FPGA. Therefore, if the DIU is going to be enabled, then memory-mapped devices on the localbus, like NOR flash, need to be disabled. This also means that the localbus is not a 'simple-bus' any more, so remove that string from the compatible node. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Xie Xiaobo 提交于
The properties indicates that the hardware supports waking up via magic packet. Signed-off-by: NXie Xiaobo <X.Xie@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Ramneek Mehresh 提交于
Add usb controller version info for the following: MPC8536, P1010, P1020, P1021, P1022, P1023, P2020, P2041, P3041, P3060, P5020 Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Xu Jiucheng 提交于
P1021RDB-PC Overview ----------------- 1Gbyte DDR3 (on board DDR) 16Mbyte NOR flash 32Mbyte eSLC NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory Real-time clock on I2C bus SD/MMC connector to interface with the SD memory card PCIex - x1 PCIe slot or x1 PCIe to dual SATA controller - x1 mini-PCIe slot USB 2.0 - ULPI PHY interface: SMSC USB3300 USB PHY and Genesys Logic’s GL850A - Two USB2.0 Type A receptacles - One USB2.0 signal to Mini PCIe slot eTSEC1: Connected to RGMII PHY VSC7385 eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY AR8021 DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by: NMatthew McClintock <msm@freescale.com> Signed-off-by: NXu Jiucheng <B37781@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 23 2月, 2012 3 次提交
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由 Kyle Moffett 提交于
The FreeScale PowerQUICC-III-compatible (mpc85xx/mpc86xx) MPICs do not correctly report the number of hardware interrupt sources, so software needs to override the detected value with "256". To avoid needing to write custom board-specific code to detect that scenario, allow it to be easily overridden in the device-tree. Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Kyle Moffett 提交于
The Freescale MPIC (and perhaps others in the future) is incapable of routing non-IPI interrupts to more than once CPU at a time. Currently all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to mpic_alloc(), but that information should really be present in the device-tree. Older board code can't rely on the device-tree having the property set, but newer platforms won't need it manually specified in the code. [BenH: Remove unrelated changes, folded in a different patch] Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Kyle Moffett 提交于
The MPIC code checks for a "big-endian" property and sets the flag MPIC_BIG_ENDIAN if one is present, although prior to the "mpic->flags" fixup that would never have worked anways. Unfortunately, even now that it works properly, the Freescale mpic device-node (the "PowerQUICC-III"-compatible one) does not specify it, so all of the board ports need to manually pass it to mpic_alloc(). Document the flag and add it to the pq3 device tree. Existing code will still need to pass the MPIC_BIG_ENDIAN flag because their dtb may not have this property, but new platforms shouldn't need to do so. Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 18 1月, 2012 1 次提交
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由 Jerry Huang 提交于
According to latest kernel, the auto-cmd12 property should be "sdhci,auto-cmd12", and according to the SDHC binding and the workaround for the special chip, add the chip compatible for eSDHC: "fsl,p1022-esdhc", "fsl,mpc8536-esdhc", "fsl,p1020-esdhc", "fsl,p2020-esdhc" and "fsl,p1010-esdhc". Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 05 1月, 2012 1 次提交
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由 Kumar Gala 提交于
The Freescale serial port's are pretty much a 16550, however there are some FSL specific bugs and features. Add a "fsl,ns16550" compatiable string to allow code to handle those FSL specific issues. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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