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  1. 20 12月, 2005 3 次提交
  3. 15 12月, 2005 2 次提交
  5. 13 12月, 2005 16 次提交
  7. 12 12月, 2005 2 次提交
  9. 10 12月, 2005 1 次提交
    • N
      [ARM] 3200/1: Singlestep over ARM BX and BLX instructions using ptrace fix · 22f975f4
      由 Nikola Valerjev 提交于 
      Patch from Nikola Valerjev

Single stepping an application using ptrace() fails over ARM instructions BX and BLX.

Steps to reproduce:

Compile and link the following files

main.c
-----
void foo();
int main() {
    foo();
    return 0;
}

foo.s
-----
	.text
	.globl foo
foo:
	BX LR

Using ptrace() functionality, run to main(), and start singlestepping.
Singlestep over \"BX LR\" instruction won\'t transfer the control back
to main, but run the code to completion.

This problems seems to be in the function get_branch_address() in
arch/arm/kernel/ptrace.c. The function doesn\'t seem to recognize BX
and BLX instructions as branches. BX and BLX instructions can be used
to convert from ARM to Thumb mode if the target address has the low
bit set. However, they are also perfectly legal in the ARM only mode.
Although other things in the kernel seem to indicate that only ARM
mode is accepted (and not Thumb), many compilers will generate BX
and BLX instructions even when generating ARM only code.
Signed-off-by: NNikola Valerjev <nikola@ghs.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      22f975f4
  11. 09 12月, 2005 3 次提交
    • D
      [PATCH] powerpc: Fix SLB flushing path in hugepage · 23ed6cb9
      由 David Gibson 提交于 
      On ppc64, when opening a new hugepage region, we need to make sure any
old normal-page SLBs for the area are flushed on all CPUs.  There was
a bug in this logic - after putting the new hugepage area masks into
the thread structure, we copied it into the paca (read by the SLB miss
handler) only on one CPU, not on all.  This could cause incorrect SLB
entries to be loaded when a multithreaded program was running
simultaneously on several CPUs.  This patch corrects the error,
copying the context information into the PACA on all CPUs using the mm
in question before flushing any existing SLB entries.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      23ed6cb9
    • D
      [PATCH] powerpc: Add missing icache flushes for hugepages · cbf52afd
      由 David Gibson 提交于 
      On most powerpc CPUs, the dcache and icache are not coherent so
between writing and executing a page, the caches must be flushed.
Userspace programs assume pages given to them by the kernel are icache
clean, so we must do this flush between the kernel clearing a page and
it being mapped into userspace for execute.  We were not doing this
for hugepages, this patch corrects the situation.

We use the same lazy mechanism as we use for normal pages, delaying
the flush until userspace actually attempts to execute from the page
in question.

Tested on G5.
Signed-off-by: NDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cbf52afd
    • O
      [PATCH] powerpc: Set cache info defaults · dabcafd3
      由 Olof Johansson 提交于 
      Cache info is setup by walking the device tree in initialize_cache_info().
However, icache_flush_range might be called before that, in
slb_initialize()->patch_slb_encoding, which modifies the load immediate
instructions used with SLB fault code.

Not only that, but depending on memory layout, we might take SLB faults
during unflatten_device_tree. So that fault will load an SLB entry that
might not contain the right LLP flags for the segment.

Either we can walk the flattened device tree to setup cache info, or
we can pick the known defaults that are known to work. Doing it in the
flattened device tree is hairier since we need to know the machine type
to know what property to look for, etc, etc.

For now, it's just easier to go with the defaults. Worst thing that
happens from it is that we might waste a few cycles doing too small
dcbst/icbi increments.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      dabcafd3
  13. 08 12月, 2005 3 次提交
  15. 07 12月, 2005 4 次提交
    • J
      [IA64-SGI] Fix SN PTC deadlock recovery · 590711b7
      由 Jack Steiner 提交于 
      The patch that added support for a new platform chipset (shub2) broke
PTC deadlock recovery on older versions of the chipset. (PTCs are the
SN platform-specific method for doing a global TLB purge). This
patch fixes deadlock recovery so that it works on both the old & new
chipsets.
Signed-off-by: NJack Steiner <steiner@sgi.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>
      590711b7
    • R
      [IA64] Change SET_PERSONALITY to comply with comment in binfmt_elf.c. · bd1d6e24
      由 Robin Holt 提交于 
      We have a customer application which trips a bug.  The problem arises
when a driver attempts to call do_munmap on an area which is mapped, but
because current->thread.task_size has been set to 0xC0000000, the call
to do_munmap fails thinking it is an unmap beyond the user's address
space.

The comment in fs/binfmt_elf.c in load_elf_library() before the call
to SET_PERSONALITY() indicates that task_size must not be changed for
the running application until flush_thread, but is for ia64 executing
ia32 binaries.

This patch moves the setting of task_size from SET_PERSONALITY() to
flush_thread() as indicated.  The customer application no longer is able
to trip the bug.
Signed-off-by: NRobin Holt <holt@sgi.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>
      bd1d6e24
    • J
      [IA64] Limit the maximum NODEDATA_ALIGN() offset · acb7f672
      由 Jack Steiner 提交于 
      The per-node data structures are allocated with strided offsets that are a
function of the node number. This prevents excessive cache-aliasing from
occurring.

On systems with a large number of nodes, the strided offset becomes
too large. This patch restricts the maximum offset to 32MB. This is far larger
than the size of any current L3 cache.
Signed-off-by: NJack Steiner <steiner@sgi.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>
      acb7f672
    • J
      [IA64-SGI] altix: pci_window fixup · 3ec829b6
      由 John Keller 提交于 
      Altix only patch to add fixup code that sets up
pci_controller->window. This code is a temporary
fix until ACPI support on Altix is added.

Also, corrects the usage of pci_dev->sysdata,
which had previously been used to reference
platform specific device info, to now point to
a pci_controller struct.
Signed-off-by: NJohn Keller <jpk@sgi.com>
Signed-off-by: NTony Luck <tony.luck@intel.com>
      3ec829b6
  17. 06 12月, 2005 1 次提交
  19. 05 12月, 2005 3 次提交
  21. 03 12月, 2005 2 次提交