Skip to content

R
raspberrypi-kernel

openeuler / raspberrypi-kernel

通知 13
Star 1
Fork 0
R
raspberrypi-kernel
切换分支/标签
  1. 21 10月, 2014 17 次提交
  3. 06 10月, 2014 4 次提交
  5. 30 8月, 2014 1 次提交
  7. 14 8月, 2014 18 次提交
    • M
      xtensa: deprecate fast_xtensa and fast_spill_registers syscalls · 9184289c
      由 Max Filippov 提交于 
      These syscalls are not used by userspace tools for some time now, and
they have issues when called with invalid arguments. It's not worth
changing signal delivery mechanism as we don't expect any new users for
these syscalls. Let's keep them for backwards compatibility under #ifdef,
disabled by default.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      9184289c
    • M
      xtensa: don't allow overflow/underflow on unaligned stack · 3cfc096e
      由 Max Filippov 提交于 
      Double exceptions that happen during register window overflow/underflow
are handled in the topmost stack frame, as if it was the only exception
that occured. However unaligned access exception handler is special
because it needs to analyze instruction that caused the exception, but
the userspace instruction that triggered window exception is completely
irrelevant. Unaligned data access is rather normal in the generic
userspace code, but stack pointer manipulation must always be done by
architecture-aware code and thus unaligned stack means a serious problem
anyway.
Use the default unaligned access handler that raises SIGBUS in case
of unaligned access in window overflow/underflow handler.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      3cfc096e
    • M
      xtensa: fix a6 and a7 handling in fast_syscall_xtensa · d1b6ba82
      由 Max Filippov 提交于 
      Remove restoring a6 on some return paths and instead modify and restore
it in a single place, using symbolic name.
Correctly restore a7 from PT_AREG7 in case of illegal a6 value.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      d1b6ba82
    • M
      xtensa: allow single-stepping through unaligned load/store · a83b02e9
      由 Max Filippov 提交于 
      Update icount when icountlevel is non-zero but not greater than EXCM level
when load/store instruction is successfully emulated. This allows
single-stepping over such instruction in userspace debugger.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      a83b02e9
    • M
      xtensa: move invalid unaligned instruction handler closer to its users · 21570465
      由 Max Filippov 提交于 
      With this change a threaded jump from .Linvalid_instruction_load to
.Linvalid_instruction can be removed and more code may be added to
common load/store exit path.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      21570465
    • M
      xtensa: make fast_unaligned store restartable · e9500dd8
      由 Max Filippov 提交于 
      fast_unaligned may encounter DTLB miss or SEGFAULT during the store
emulation. Don't update epc1 and lcount until after the store emulation
is complete, so that the faulting store instruction could be replayed.
Remove duplicate code handling zero overhead loops and calculate new
epc1 and lcount in one place.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      e9500dd8
    • M
      xtensa: add double exception fixup handler for fast_unaligned · c3ef1f4d
      由 Max Filippov 提交于 
      fast_unaligned_fixup restores user registers and runs normal exception
handler in the current stack frame. Unaligned load/store is retried
after that.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      c3ef1f4d
    • M
      xtensa: fix kernel/user jump out of fast_unaligned · a450dc69
      由 Max Filippov 提交于 
      Use correct register (a0, just read from the PS) to check user mode bit.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      a450dc69
    • M
      xtensa: configure kc705 for highmem · b82837c7
      由 Max Filippov 提交于 
      Enable all memory available on KC705 (1G - 128M) by default. Update memory
node in DTS and also limit usable memory in bootargs in case memmap is
passed from the bootloader.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      b82837c7
    • M
      xtensa: support highmem in aliasing cache flushing code · 270eec76
      由 Max Filippov 提交于 
      Use __flush_invalidate_dcache_page_alias with alias set to color of the
page physical address instead of __flush_invalidate_dcache_page: this
works for high memory pages and mapping/unmapping to the TLBTEMP area is
virtually free.

Allow building configurations with aliasing cache and highmem enabled.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      270eec76
    • M
      xtensa: support aliasing cache in kmap · 8504b503
      由 Max Filippov 提交于 
      Define ARCH_PKMAP_COLORING and provide corresponding macro definitions
on cores with aliasing data cache.

Instead of single last_pkmap_nr maintain an array last_pkmap_nr_arr of
pkmap counters for each page color. Make sure that kmap maps physical
page at virtual address with color matching its physical address.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      8504b503
    • M
      xtensa: support aliasing cache in k[un]map_atomic · 32544d9c
      由 Max Filippov 提交于 
      Map high memory pages at virtual addresses with color that match color
of their physical address. Existing cache alias management mechanisms
may be used with such pages.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      32544d9c
    • M
      xtensa: implement clear_user_highpage and copy_user_highpage · a91902db
      由 Max Filippov 提交于 
      Existing clear_user_page and copy_user_page cannot be used with highmem
because they calculate physical page address from its virtual address
and do it incorrectly in case of high memory page mapped with
kmap_atomic. Also kmap is not needed, as most likely userspace mapping
color would be different from the kmapped color.

Provide clear_user_highpage and copy_user_highpage functions that
determine if temporary mapping is needed for the pages. Move most of the
logic of the former clear_user_page and copy_user_page to
xtensa/mm/cache.c only leaving temporary mapping setup, invalidation and
clearing/copying in the xtensa/mm/misc.S. Rename these functions to
clear_page_alias and copy_page_alias.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      a91902db
    • M
      xtensa: fix TLBTEMP_BASE_2 region handling in fast_second_level_miss · 7128039f
      由 Max Filippov 提交于 
      Current definition of TLBTEMP_BASE_2 is always 32K above the
TLBTEMP_BASE_1, whereas fast_second_level_miss handler for the TLBTEMP
region analyzes virtual address bit (PAGE_SHIFT + DCACHE_ALIAS_ORDER)
to determine TLBTEMP region where the fault happened. The size of the
TLBTEMP region is also checked incorrectly: not 64K, but twice data
cache way size (whicht may as well be less than the instruction cache
way size).

Fix TLBTEMP_BASE_2 to be TLBTEMP_BASE_1 + data cache way size.
Provide TLBTEMP_SIZE that is a greater of doubled data cache way size or
the instruction cache way size, and use it to determine if the second
level TLB miss occured in the TLBTEMP region.

Practical occurence of page faults in the TLBTEMP area is extremely
rare, this code can be tested by deletion of all w[di]tlb instructions
in the tlbtemp_mapping region.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      7128039f
    • M
      xtensa: allow fixmap and kmap span more than one page table · dec7305d
      由 Max Filippov 提交于 
      To support aliasing cache both kmap region sizes are multiplied by the
number of data cache colors. After that expansion page tables that cover
kmap regions may become larger than one page. Correctly allocate and
initialize page tables in this case.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      dec7305d
    • M
      xtensa: make fixmap region addressing grow with index · 22def768
      由 Max Filippov 提交于 
      It's much easier to reason about alignment and coloring of regions
located in the fixmap when fixmap index is just a PFN within the fixmap
region. Change fixmap addressing so that index 0 corresponds to
FIXADDR_START instead of the FIXADDR_TOP.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      22def768
    • M
      xtensa: fix access to THREAD_RA/THREAD_SP/THREAD_DS · 52247123
      由 Max Filippov 提交于 
      With SMP and a lot of debug options enabled task_struct::thread gets out
of reach of s32i/l32i instructions with base pointing at task_struct,
breaking build with the following messages:

  arch/xtensa/kernel/entry.S: Assembler messages:
  arch/xtensa/kernel/entry.S:1002: Error: operand 3 of 'l32i.n' has invalid value '1048'
  arch/xtensa/kernel/entry.S:1831: Error: operand 3 of 's32i.n' has invalid value '1040'
  arch/xtensa/kernel/entry.S:1832: Error: operand 3 of 's32i.n' has invalid value '1044'

Change base to point to task_struct::thread in such cases.
Don't use a10 in _switch_to to save/restore prev pointer as a2 is not
clobbered.

Cc: stable@vger.kernel.org
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      52247123
    • M
      xtensa: add renameat2 syscall · 89f77c6f
      由 Miklos Szeredi 提交于 
      Signed-off-by: NMiklos Szeredi <mszeredi@suse.cz>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
      89f77c6f