1. 08 3月, 2010 1 次提交
  2. 05 3月, 2010 2 次提交
  3. 01 3月, 2010 4 次提交
    • A
      KVM: PPC: Keep SRR1 flags around in shadow_msr · f7adbba1
      Alexander Graf 提交于
      SRR1 stores more information that just the MSR value. It also stores
      valuable information about the type of interrupt we received, for
      example whether the storage interrupt we just got was because of a
      missing htab entry or not.
      
      We use that information to speed up the exit path.
      
      Now if we get preempted before we can interpret the shadow_msr values,
      we get into vcpu_put which then calls the MSR handler, which then sets
      all the SRR1 information bits in shadow_msr to 0. Great.
      
      So let's preserve the SRR1 specific bits in shadow_msr whenever we set
      the MSR. They don't hurt.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      f7adbba1
    • A
      KVM: PPC: Export __giveup_vsx · fbad5f1d
      Alexander Graf 提交于
      We need to explicitly only giveup VSX in KVM, so let's export that
      specific function to module space.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      fbad5f1d
    • A
      KVM: PPC: Call SLB patching code in interrupt safe manner · 021ec9c6
      Alexander Graf 提交于
      Currently we're racy when doing the transition from IR=1 to IR=0, from
      the module memory entry code to the real mode SLB switching code.
      
      To work around that I took a look at the RTAS entry code which is faced
      with a similar problem and did the same thing:
      
        A small helper in linear mapped memory that does mtmsr with IR=0 and
        then RFIs info the actual handler.
      
      Thanks to that trick we can safely take page faults in the entry code
      and only need to be really wary of what to do as of the SLB switching
      part.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      021ec9c6
    • A
      KVM: PPC: Use PACA backed shadow vcpu · 7e57cba0
      Alexander Graf 提交于
      We're being horribly racy right now. All the entry and exit code hijacks
      random fields from the PACA that could easily be used by different code in
      case we get interrupted, for example by a #MC or even page fault.
      
      After discussing this with Ben, we figured it's best to reserve some more
      space in the PACA and just shove off some vcpu state to there.
      
      That way we can drastically improve the readability of the code, make it
      less racy and less complex.
      Signed-off-by: NAlexander Graf <agraf@suse.de>
      Signed-off-by: NAvi Kivity <avi@redhat.com>
      7e57cba0
  4. 26 2月, 2010 1 次提交
  5. 24 2月, 2010 1 次提交
  6. 23 2月, 2010 2 次提交
  7. 19 2月, 2010 3 次提交
  8. 18 2月, 2010 1 次提交
  9. 17 2月, 2010 7 次提交
    • D
      powerpc/booke: Add support for advanced debug registers · 3bffb652
      Dave Kleikamp 提交于
      powerpc/booke: Add support for advanced debug registers
      
      From: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
      
      Based on patches originally written by Torez Smith.
      
      This patch defines context switch and trap related functionality
      for BookE specific Debug Registers. It adds support to ptrace()
      for setting and getting BookE related Debug Registers
      Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com>
      Cc: Torez Smith  <lnxtorez@linux.vnet.ibm.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: David Gibson <dwg@au1.ibm.com>
      Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
      Cc: Kumar Gala <galak@kernel.crashing.org>
      Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
      Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
      Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      3bffb652
    • D
      powerpc: Extended ptrace interface · 3162d92d
      Dave Kleikamp 提交于
      powerpc: Extended ptrace interface
      
      From: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
      
      Based on patches originally written by Torez Smith.
      
      Add a new extended ptrace interface so that user-space has a single
      interface for powerpc, without having to know the specific layout
      of the debug registers.
      
      Implement:
      PPC_PTRACE_GETHWDEBUGINFO
      PPC_PTRACE_SETHWDEBUG
      PPC_PTRACE_DELHWDEBUG
      Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com>
      Acked-by: NDavid Gibson <dwg@au1.ibm.com>
      Cc: Torez Smith  <lnxtorez@linux.vnet.ibm.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
      Cc: Kumar Gala <galak@kernel.crashing.org>
      Cc: Sergio Durigan Junior <sergiodj@br.ibm.com>
      Cc: Thiago Jung Bauermann <bauerman@br.ibm.com>
      Cc: linuxppc-dev list <Linuxppc-dev@ozlabs.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      3162d92d
    • D
      powerpc/booke: Introduce new CONFIG options for advanced debug registers · 172ae2e7
      Dave Kleikamp 提交于
      powerpc/booke: Introduce new CONFIG options for advanced debug registers
      
      From: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
      
      Introduce new config options to simplify the ifdefs pertaining to the
      advanced debug registers for booke and 40x processors:
      
      CONFIG_PPC_ADV_DEBUG_REGS - boolean: true for dac-based processors
      CONFIG_PPC_ADV_DEBUG_IACS - number of IAC registers
      CONFIG_PPC_ADV_DEBUG_DACS - number of DAC registers
      CONFIG_PPC_ADV_DEBUG_DVCS - number of DVC registers
      CONFIG_PPC_ADV_DEBUG_DAC_RANGE - DAC ranges supported
      
      Beginning conservatively, since I only have the facilities to test 440
      hardware.  I believe all 40x and booke platforms support at least 2 IAC
      and 2 DAC registers.  For 440, 4 IAC and 2 DVC registers are enabled, as
      well as the DAC ranges.
      Signed-off-by: NDave Kleikamp <shaggy@linux.vnet.ibm.com>
      Acked-by: NDavid Gibson <dwg@au1.ibm.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      172ae2e7
    • A
      powerpc: Convert global "BAD" interrupt to per cpu spurious · 17081102
      Anton Blanchard 提交于
      I often get asked if BAD interrupts are really bad. On some boxes (eg
      IBM machines running a hypervisor) there are valid cases where are
      presented with an interrupt that is not for us. These cases are common
      enough to show up as thousands of BAD interrupts a day.
      
      Tone them down by calling them spurious. Since they can be a significant cause
      of OS jitter, we may as well log them per cpu so we know where they are
      occurring.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      17081102
    • A
      powerpc: Add timer, performance monitor and machine check counts to /proc/interrupts · 89713ed1
      Anton Blanchard 提交于
      With NO_HZ it is useful to know how often the decrementer is going off. The
      patch below adds an entry for it and also adds it into the /proc/stat
      summaries.
      
      While here, I added performance monitoring and machine check exceptions.
      I found it useful to keep an eye on the PMU exception rate
      when using the perf tool. Since it's possible to take a completely
      handled machine check on a System p box it also sounds like a good idea to
      keep a machine check summary.
      
      The event naming matches x86 to keep gratuitous differences to a minimum.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      89713ed1
    • A
      powerpc: Rework /proc/interrupts · c86845ed
      Anton Blanchard 提交于
      On a large machine I noticed the columns of /proc/interrupts failed to line up
      with the header after CPU9. At sufficiently large numbers of CPUs it becomes
      impossible to line up the CPU number with the counts.
      
      While fixing this I noticed x86 has a number of updates that we may as well
      pull in. On PowerPC we currently omit an interrupt completely if there is no
      active handler, whereas on x86 it is printed if there is a non zero count.
      
      The x86 code also spaces the first column correctly based on nr_irqs.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      c86845ed
    • A
      powerpc: Reduce footprint of irq_stat · 8c007bfd
      Anton Blanchard 提交于
      PowerPC is currently using asm-generic/hardirq.h which statically allocates an
      NR_CPUS irq_stat array. Switch to an arch specific implementation which uses
      per cpu data:
      
      On a kernel with NR_CPUS=1024, this saves quite a lot of memory:
      
         text    data     bss      dec         hex    filename
      8767938 2944132 1636796 13348866         cbb002 vmlinux.baseline
      8767779 2944260 1505724 13217763         c9afe3 vmlinux.irq_cpustat
      
      A saving of around 128kB.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8c007bfd
  10. 14 2月, 2010 3 次提交
  11. 09 2月, 2010 12 次提交
  12. 04 2月, 2010 1 次提交
  13. 03 2月, 2010 2 次提交