Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

With the recent entry.S refactoring, the SH-X3 path had a mov.l for a
register to register copy, resulting in:

  AS      arch/sh/kernel/cpu/sh4/../sh3/entry.o
arch/sh/kernel/cpu/sh4/../sh3/entry.S: Assembler messages:
arch/sh/kernel/cpu/sh4/../sh3/entry.S:366: Error: invalid operands for opcode
make[3]: *** [arch/sh/kernel/cpu/sh4/../sh3/entry.o] Error 1

Switch it over to a mov to fix it up.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Prefetch early exception data. There is unused space in our
exception handler cache line anyway, so this is almost free.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Remove EXPEVT vector from the stack, lookup_exception_vector()
for sh3/sh4/sh4a is already using k2 to get the vector.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch reworks the sh3/sh4/sh4a register restore code in
the following ways:
 - break out restore_regs() from restore_all()
 - the register saving order is unchanged
 - use restore_regs() in sh_bios_handler and restore_all
 - document the function
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch reworks the sh3/sh4/sh4a register saving code in
the following ways:
 - break out prepare_stack_save_dsp() from handle_exception()
 - break out save_regs() from handle_exception()
 - the register saving order is unchanged
 - align new functions to fit in cache lines
 - separate exception code from interrupt code
 - keep main code flow in a single cache line per exception vector
 - use bsr/rts for regular functions (save pr first)
 - keep data in one shared cache line (exception_data)
 - document the functions
 - tie in the hp6xx code
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This migrates from the old bitrotted kgdb stub implementation and moves
to the generic stub. In the process support for SH-2/SH-2A is also added,
which the old stub never provided.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The INTEVT read at interrupt exception entry is uneccessary, as the read
is deferred until we are ready to enter do_IRQ(). The kgdb nmi path still
requires it, so move it there.
Signed-off-by: NAoi Shinkai <shinkoi2005@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch adds pinmux and gpio support for the sh7720 processor.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This follows the sparc changes a439fe51.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.
Signed-off-by: NSam Ravnborg <sam@ravnborg.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Clean up the intc tables by removing unneeded #ifdefs. The vector
list is what selects which interrupt sources that should be added,
having unsupported bitfields listed is ok as long as the vector
is excluded from the list.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch adds interrupt acknowledge code for external interrupt
sources on sh3 processors. Only really required for edge triggered
interrupts, but we ack regardless of sense configuration.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch unifies the sh3 external irq pin code. It buys us some
savings with reduced code redundancy, but the main feature with
this change is irq sense selection support for all sh3 processors.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Fix sh7705 interrupt sources for vectors 0xc80 and 0xca0.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This header is needed on other architectures as well (namely h8300),
which currently fails to build without this in place. Rather than
duplicating the port definition completely there, just move this to a
common location instead.

This should get h8300 working again for 2.6.25, in addition to the
changes already pushed by Sato-san in -rc2.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Fix the RTC resources setup for sh770x. Whit these proper
start values RTC driver (drivers/rtc/rtc-sh.c) works.
Signed-off-by: NRafael Ignacio Zurita <rizurita@yahoo.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

drivers/char/pcmcia/synclink_cs.c:284:1: warning: "CCR3" redefined
In file included from include/asm/cache.h:13,
                 from include/asm/processor_32.h:15,
                 from include/asm/processor.h:60,
                 from include/linux/prefetch.h:14,
                 from include/linux/list.h:8,
                 from include/linux/module.h:9,
                 from drivers/char/pcmcia/synclink_cs.c:38:
include/asm/cpu/cache.h:38:1: warning: this is the location of the previous definition
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch removes interrupt priority tables from the intc code.
Optimal priority assignment varies with embedded application anyway,
so keeping the interrupt priority tables together with cpu-specific
code doesn't make sense.

The function intc_set_priority() should be used instead to set the
desired interrupt priority level.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch provides specific clock support for the SH7712.
Signed-off-by: NAndrew Murray <amurray@mpc-data.co.uk>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Presently most of the 29-bit physical parts do P1/P2 segmentation
with a 1:1 cached/uncached mapping, jumping between the two to
control the caching behaviour. This provides the basic infrastructure
to maintain this behaviour on 32-bit physical parts that don't map
P1/P2 at all, using a shiny new linker section and corresponding
fixmap entry.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements kernel-level atomic rollback built on top of gUSA,
as an alternative non-IRQ based atomicity method. This is generally
a faster method for platforms that are lacking the LL/SC pairs that
SH-4A and later use, and is only supportable on legacy cores.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NKieran Bingham <kbingham@mpc-data.co.uk>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This was all reworked some time ago, the old debug_enter was ripped
out with everything going through a debug trap jump table instead.
Kill off the debug_enter target and reference kgdb_handle_exception
directly.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This moves off of smp_processor_id() and only sets the probe
information for the boot CPU directly. This will be copied out
for the secondaries, so there's no reason to do this each time.

This also allows for some header tidying.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

With the intc core improved it is now possible to put the intc data
structures in the initdata section.

Version two of this patch puts the __initdata inside DECLARE_INTC_DESC()
and removes the __initdata included in the board specific r2d code.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

We need a secondary register member in struct intc_prio_reg to support
dual priority registers used by ipi on x3.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for the SH7720 (SH3-DSP) CPU.

Signed-off by: Markus Brunner <super.firetwister@gmail.com>
Signed-off by: Mark Jonas <toertel@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch removes redundant interrupt code for the shmin board which
is using a sh770x processor and 4 IRQ lines as individual interrupts
(IRQ-mode).
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

All SH-4 parts have a 4-digit year, while the SH-3 parts typically
only use a 2-digit one. The SH7705, SH7710, and SH7712 SH-3 parts
however opted to extend it to 4-digit and still look and act like
an SH-3 RTC in all other ways.

This adds a capability flag (RTC_CAP_4_DIGIT_YEAR) that these
corner-case CPU subtypes can set in their platform data and cleans
up some of the ifdef mess in the driver as a result.
Reported-by: NMarkus Brunner <super.firetwister@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The intc tables for sh3 currently contain a typo where the bit
fields in IPRD are mixed up for IRQ4 and IRQ5. This patch makes
sure the correct bit fields are used - all according to the
datasheets.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch makes sure that the sh7710 specific ipsec vector is missing
if building for a sh7712. All according to the datasheet.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch adds a few missing vectors for sh7707. The only interrupt
controller differences between sh7707 and sh7709 seem to be added
vectors for one LCD controller and two PCMCIA slots.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch unifies the cpu specific interrupt setup code for
sh7706, sh7707, sh7708 and sh7709 and moves the code into a new
file called setup-sh770x.c.  It makes sense to share the setup code
between these processors because most hardware blocks are identical
from a software point of view. With this patch the sh770x processors
now have a complete set of vectors that match with the information
provided by the data sheets. This is a big improvement for sh7708.

Vectors for IRQ4 and IRQ5 are enabled by default. Use
plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.

This patch also unifies the platform device setup code which means
that the rtc driver now has platform data for all sh770x processors.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code
for sh7710 from ipr to intc. While at it new vectors are added
to match the information provided by the datasheet. Version two
simplifies the Kconfig part.

Vectors for IRQ4 and IRQ5 are enabled by default. Use
plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.

This patch also adds sh7710 specific platform data for the rtc
driver. The base address of SCIF1 is adjusted to match the
datasheet.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch converts the cpu specific interrupt setup code for
sh7705 from ipr to intc. While at it new vectors are added to
match the information provided by the datasheet.

Vectors for IRQ4 and IRQ5 are enabled by default.

Use plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode.

This patch also adds sh7705 specific platform data for the rtc driver.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

In the SH-3/4 TLB access violation path we were enabling IRQs before
the call in to trace_hardirqs_on(), which ended up triggering:

        if (DEBUG_LOCKS_WARN_ON(!irqs_disabled()))
                return;

in kernel/lockdep.c:2031. Fix this up by removing the early re-enable,
we were already re-enabling IRQs post-trace_hardirqs_on() already, so
the semantics are now as was initially intended.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>