This removes a bunch of "extern" declarations and CONFIG_SMP ifdefs.
Signed-off-by: NKyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>

85xx board files have a lot of duplication in *_publish_devices()/
*_declare_of_platform_devices() functions. Merge that into a single
function common to most of the boards.
Signed-off-by: NDmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Separate handling of CPM2 PIC initialization to mpc85xx_cpm2_pic_init()
function.
Signed-off-by: NDmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Change the string to check for CAMP mode boot on MPC85xx (eg. P2020) to match
the one in the corresponding dts files (p2020rdb_camp_core{0,1}.dts).

Without this fix the mpic is configured as in the SMP boot mode, which causes
the first core to report a protected source interrupt error for devices
of the other core and lock up.

Also add MPIC_SINGLE_DEST_CPU on both P2020 based architectures in CAMP
mode as suggested by Scott Wood. Thanks.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NFabio Baltieri <fabio.baltieri@gmail.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).

From board perspective P1020RDB is same as P2020RDB.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch creates the dts files for each core and splits the devices
between the two cores for P2020RDB.

core0 has memory, L2, i2c, spi, dma1, usb, eth0, eth1, crypto,
		global-util, pci0,
core1 has L2, dma2, eth0, pci1, msi.

MPIC is shared between two cores but each core will protect its
interrupts from other core by using "protected-sources" of mpic.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for the P2020RDB reference board from Freescale.

Overview of P2020RDB platform
	- DDR
	  DDR2 1G
	- NOR Flash
	  16MByte
	- NAND Flash
	  32MByte
	- 3 Ethernet interfaces
	  1) etSEC1
		- RGMII
		- connected to a 5 port Vitesse Switch(VSC7385)
		- Switch is memory mapped through eLBC interface(CS#2)
		- IRQ1
	  2) etSEC2
		- SGMII
		- connected to VSC8221
		- IRQ2
	  3) etSEC3
		- RGMII
		- connected to VSC8641
		- IRQ3
	- 2 1X PCIe interfaces
	- SD/MMC ,USB
	- SPI EEPROM
	- Serial I2C EEPROM
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add the platform-specific code for enabling SWIOTLB if needed on P2020DS,
MPC85xx DS, and MPC85xx MDS boards as they are capable of having >4G of
memory.

We determine if we need to enable swiotlb based on how much memory is in
the board and if it exceeds 4G or what we can map via PCI inbound
windows.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Currently it doesn't matter where the mdio nodes are placed, but with
power management support (i.e. when sleep = <> properties will take
effect), mdio nodes placement will become important: mdio controller
is a part of the ethernet block, so the mdio nodes should be placed
correctly. Otherwise we may wrongly assume that MDIO controllers are
available during sleep.
Suggested-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

add simple-bus compatible property to soc nodes for 83xx/85xx platforms
that were missing them.  Add same to platform probe code.

This fixes SoC device drivers (such as talitos) to succeed in matching
devices present in the soc node.

also update mpc836x_rdk dts to new SEC bindings (overlooked in commit
3fd44736: powerpc/fsl: update crypto node definition and device tree
instances).
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Remove the "uninitialized use" compile warning and avoid potential
runtime issue.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for the MPC8536 process and MPC8536DS reference board.  The
MPC8536 is an e500v2 based SoC which eTSEC, USB, SATA, PCI, and PCIe.

The USB and SATA IP blocks are similiar to those on the PQ2 Pro SoCs and
thus use the same drivers.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>