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  1. 11 3月, 2016 1 次提交
  3. 21 1月, 2016 2 次提交
  5. 17 1月, 2016 1 次提交
  7. 17 12月, 2015 1 次提交
  9. 29 10月, 2015 1 次提交
  11. 28 10月, 2015 2 次提交
    • V
      ARC: mm: HIGHMEM: kmap API implementation · 45890f6d
      由 Vineet Gupta 提交于 
      Implement kmap* API for ARC.

This enables
 - permanent kernel maps (pkmaps): :kmap() API
 - fixmap : kmap_atomic()

We use a very simple/uniform approach for both (unlike some of the other
arches). So fixmap doesn't use the customary compile time address stuff.
The important semantic is sleep'ability (pkmap) vs. not (fixmap) which
the API guarantees.

Note that this patch only enables highmem for subsequent PAE40 support
as there is no real highmem for ARC in pure 32-bit paradigm as explained
below.

ARC has 2:2 address split of the 32-bit address space with lower half
being translated (virtual) while upper half unstranslated
(0x8000_0000 to 0xFFFF_FFFF). kernel itself is linked at base of
unstranslated space (i.e. 0x8000_0000 onwards), which is mapped to say
DDR 0x0 by external Bus Glue logic (outside the core). So kernel can
potentially access 1.75G worth of memory directly w/o need for highmem.
(the top 256M is taken by uncached peripheral space from 0xF000_0000 to
0xFFFF_FFFF)

In PAE40, hardware can address memory beyond 4G (0x1_0000_0000) while
the logical/virtual addresses remain 32-bits. Thus highmem is required
for kernel proper to be able to access these pages for it's own purposes
(user space is agnostic to this anyways).
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      45890f6d
    • V
      ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes · 3971cdc2
      由 Vineet Gupta 提交于 
      For Run-on-reset, non masters need to spin wait. For Halt-on-reset they
can jump to entry point directly.

Also while at it, made reset vector handler as "the" entry point for
kernel including host debugger based boot (which uses the ELF header
entry point)
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      3971cdc2
  13. 17 10月, 2015 2 次提交
    • V
      ARC: mm: MMU v1..v3 only selectable for ARCompact ISA based cores · c583ee4f
      由 Vineet Gupta 提交于 
      Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      c583ee4f
    • V
      ARCv2: mm: THP support · fe6c1b86
      由 Vineet Gupta 提交于 
      MMUv4 in HS38x cores supports Super Pages which are basis for Linux THP
support.

Normal and Super pages can co-exist (ofcourse not overlap) in TLB with a
new bit "SZ" in TLB page desciptor to distinguish between them.
Super Page size is configurable in hardware (4K to 16M), but fixed once
RTL builds.

The exact THP size a Linx configuration will support is a function of:
 - MMU page size (typical 8K, RTL fixed)
 - software page walker address split between PGD:PTE:PFN (typical
   11:8:13, but can be changed with 1 line)

So for above default, THP size supported is 8K * 256 = 2M

Default Page Walker is 2 levels, PGD:PTE:PFN, which in THP regime
reduces to 1 level (as PTE is folded into PGD and canonically referred
to as PMD).

Thus thp PMD accessors are implemented in terms of PTE (just like sparc)
Signed-off-by: NVineet Gupta <vgupta@synopsys.com>
      fe6c1b86
  15. 20 8月, 2015 1 次提交
  17. 11 8月, 2015 1 次提交
  19. 04 8月, 2015 1 次提交
  21. 23 7月, 2015 1 次提交
  23. 20 7月, 2015 1 次提交
  25. 06 7月, 2015 1 次提交
  27. 25 6月, 2015 1 次提交
  29. 22 6月, 2015 7 次提交
  31. 19 6月, 2015 6 次提交
  33. 03 11月, 2014 1 次提交
  35. 13 10月, 2014 3 次提交
  37. 08 4月, 2014 1 次提交
  39. 20 2月, 2014 1 次提交
  41. 24 1月, 2014 1 次提交
  43. 16 1月, 2014 1 次提交
  45. 25 11月, 2013 1 次提交
  47. 15 11月, 2013 1 次提交