am33xx has a INTC_PENDING_IRQ3 register that is not checked for pending
interrupts. This patch adds AM33XX to the ifdef of SOCs that have to
check this register.

Cc: stable@vger.kernel.org
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NTony Lindgren <tony@atomide.com>

AM43x has 224 interrupts and 7 banks, make it as maximum values. Keep
default values as earlier, if am43x is detected, update interrupts and
banks accordingly.

Also AM43x has only one cpu, ensure that clearing bitmask at wakeupgen
is done only for the single existing cpu, existing code assumes that
there are two cpu's.

If bitmask is cleared in wakeupgen for the nonexistent second cpu,
an imprecise abort happens as soon as Kernel switches to user space.
It was rootcaused by Sekhar Nori <nsekhar@ti.com>.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

OMAP3 PM core requires IVA2 bootmode to be set to idle during init. Currently,
a direct register write is used for this. Add a new ctrl API for this purpose
instead.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

OMAP3 PM code for off-mode currently saves the scratchpad contents for CM
registers within OMAP control module driver. However, as we are separating
CM code into its own driver, this must be moved also. This patch adds a
new API for saving the CM scratchpad contents and uses this from the high
level scratchpad save function.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

McBSP driver require special hacks to enable/disable the autoidle feature
for its interface clock for the proper function of the sidetone hardware.
Currently the driver just writes CM registers directly, which should be
avoided. Thus, changed the driver to use the new deny/allow_autoidle
clock API calls.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Some drivers require direct access to the autoidle functionality of the
interface clocks. Added clock APIs for these, so that the drivers do not
need to access CM registers directly.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Users of the CM funtionality should not access the CM registers directly
by themselves. Thus, added new CM driver APIs for the OMAP2 specific
functionalities which support the existing direct register accesses, and
changed the platform code to use these. This is done in preparation
for moving the CM code into its own individual driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add hwmod data for qspi for AM437x.
Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add hwmod for USBSS and the OCP2SCP for AM437x.
AM437x has got 2 instances of USBSS.
Signed-off-by: NGeorge Cherian <george.cherian@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Initialise AM43x HWMOD, powerdomains and clockdomains.
Signed-off-by: NAmbresh K <ambresh@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Build AM43x power domain, clock domain and hwmod data.

Many of AM43x IP's and interconnects are similar as that in AM335x,
hence AM335x hwmod data is being reused with necessary changes.

Earlier the plan was to reuse AM335x specific PRCM code, but as AM43x
PRCM register layout is much similar to OMAP4/5, AM335x PRCM is
divorced and instead married with OMAP4/5 PRCM for AM43x.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Reuse OMAP4 operations on AM43x.

Context related ops are not used on AM43x, as this would not add value
when using DT and AM43x is DT only boot. This additionally helps not to
add context register offset for each hwmod.
Signed-off-by: NAmbresh K <ambresh@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add hwmod support for IP's that are present in AM43x, but not in AM335x.
AM43x additional ones added here are,
1. synctimer
2. timer8-11
3. ehrpwm3-5
4. spi2-4
5. gpio4-5

AM43x pruss interconnect which is different as compared to AM335x, has
been taken care.

And register offsets for same hwmod's shared with AM335x is different,
AM43x register offsets are updated appropriately.

ocp clock of those in l4_wkup is fed from "sys_clkin_ck" instead of
"dpll_core_m4_div2_ck", so "ocpif" for those in AM43x l4_wkup has been
added seperately.

hwmod's has been added for those that have main clock (wkup_m3, control,
gpio0) and clock domain (l4_hs) different from AM335x. debugss and
adc_tsc that have different clocks and clockdomains repectively has not
been added due to the reasons mentioned below.

AM43x also has IP's like qspi, hdq1w, vpfe, des, rng, usb, dss, debugss,
adc_tsc. These are not handled here due to both/either of following
reasons,
1. To avoid churn; most of them don't have DT bindings, which would
   necessitate adding address space in hwmod, which any way would have
   to be removed once DT bindings happen with driver support.
2. patches would come in from sources other than the author
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add the data file to describe clock domains in AM43x SoC.
OMAP4 clockdomain operations is being reused here.
Signed-off-by: NAmbresh K <ambresh@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add the data file to describe all power domains in AM43x SoC.
OMAP4 powerdomain operations is being reused here.
Signed-off-by: NAmbresh K <ambresh@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add AM43x CMINST, CDOFFS, RM_RSTST & RM_RSTCTRL definitions - minimal
ones that would be used.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Hwmod common to AM43x and AM335x has register offsets different. It is
now updated based on SoC detection at run time, hence remove statically
initialized ones.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Most of IP's in AM335x is present on AM43x and so in those cases both
will use same hwmod database (except for a few cases where clock related
details differ), but there is difference w.r.t register offset between
these. Update register offsets at runtime based on the SoC detected to
help in sharing otherwise same hwmod.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

AM335x and AM43x have most of the IP's and interconnect's similar.
Instead of adding redundant hwmod data, move interconnects and hwmod
similar between AM335x and AM43x to a common location. This helps in
reuse on AM43x.

AM335x interconnects that has difference and not present in AM43x are
not moved. ocp clock of those in l4_wkup is fed from a different source
for AM43x. Also pruss interconnect is different.

AM335x hwmod's that has difference other than prcm register offsets
(difference is in clocks of wkup_m3, control, gpio0, debugss and clock
domain of l4_hs, adc_tsc as compared to AM43x) and those that are not
present in AM43x are not moved.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Most of the AM43x CM reg address offsets are with MSB bit '1' (on
16-bit value) leading to arithmetic miscalculations while calculating
CLOCK ENABLE register's address because cm_inst field was a type of
"const s16", so make it "const u16".

Also modify relevant functions so as to take care of the above.

[afzal@ti.com: fixup and cleanup]
Signed-off-by: NAnkur Kishore <a-kishore@ti.com>
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Acked-by: NRajendra Nayak <rnayak@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Otherwise we can get an error with some configs:

arch/arm/mach-omap2/timer.c:73: undefined reference to `omap_smc1'
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add this hwmod data to allow USB3 to work in OMAP5 boards.
Signed-off-by: NBenoit Cousson <bcousson@baylibre.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>
[tony@atomide.com: updated to apply against Paul's changes]
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other non-DT guest
OS. This register must be set to the right value by the
secure rom code. Setting this register helps in propagating the right
frequency value across OSes.

More discussions and the reason for adding this in a non-DT
way can be seen from below.
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html

So configuring this secure register for all the cpus here.

Cc: Nishanth Menon <nm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Tested-by: NNishanth Menon <nm@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add RNG hwmod data for AM33xx SoC.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Now that we have DT bindings to specify which devices should not
be reset and idled during init, make hwmod extract the information
(and store them in internal flags) from Device tree.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

For modules/IPs/hwmods which do not have
-1- sys->class->reset()
and
-2- hardreset lines
and
-3- No way to do an ocp reset (no sysc control)
the flag 'HWMOD_INIT_NO_RESET' is not much useful.

Cleanup all such instances across various hwmod data files.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add the missing sysc configuration to the AM335 spinlock hwmod
data. This ensures that smart-idle is enabled whenever the module
is enabled by the driver.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add the hwmod data for the spinlock IP in OMAP5 SoC.
This is needed to be able to enable the OMAP spinlock
support for OMAP5.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

Add hwmod data for High Speed USB host and TLL modules

CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

This patch adds Synchronous Serial Interface (SSI) hwmod support for
OMAP34xx SoCs.
Signed-off-by: NSebastian Reichel <sre@debian.org>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The hwmod init sequence involves initializing and idling all the
hwmods during bootup. If a module class has sysconfig, the init
sequence utilizes the module register base for performing any
sysc configuration.

The module address space is being removed from hwmod database and
retrieved from the <reg> property of the corresponding DT node.
If a hwmod does not have its corresponding DT node defined and the
memory address space is not defined in the corresponding
omap_hwmod_ocp_if, then the module register target address space
would be NULL and any sysc programming would result in a NULL
pointer dereference and a kernel boot hang.

Handle this scenario by checking for a valid module address space
during the _init of each hwmod, and leaving it in the registered
state if no module register address base is defined in either of
the hwmod data or the DT data.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: NNishanth Menon <nm@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
[paul@pwsan.com: use -ENXIO rather than -ENOMEM to indicate a missing address
 space error; fixed checkpatch.pl problem]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

OMAP5 ES1.0 was intended as a test chip and has major register level
differences w.r.t ES2.0 revision of the chip. All register defines,
dts support has been solely added for ES2.0 version of the chip.
Further, all ES1.0 chips and platforms are supposed to have been
removed from circulation. Hence, there is no need to further retain
any resemblence of ES1.0 support in id detection code.

Remove the omap_revision handling and BUG() instead to prevent folks
who mistakenly try an older unsupported chip and report bogus errors.
Signed-off-by: NNishanth Menon <nm@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.

The ratio registers are missing for a sys-clk of 20MHZ which is used
by DRA7 socs. So because of this, the counter was getting wrongly
programmed for a sys-clk of 38.4Mhz(default). So adding the ratio
registers for 20MHZ sys-clk.
Tested-by: NNishanth Menon <nm@ti.com>
Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Move omap_vout device creation inside the omap_display_init so that we can
correctly create the device based on the presence of omapdss within the
platform.

For example, on a kernel image supporting multiple platforms, omap_init_vout
will create a omapdrm platform device on a AM33xx platform even though it
doesn't have a DSS block.
Signed-off-by: NArchit Taneja <archit@ti.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Move omapfb and omapvrfb device creation inside the omap_display_init so that
we can correctly create the device based on the presence of omapdss within the
platform.

For example, on a kernel image supporting multiple platforms, omap_init_vrfb and
omap_init_fb will create omapvrfb and omapfb platform devices respectively on a
AM33xx platform even though it doesn't have a VRFB or DSS block.
Signed-off-by: NArchit Taneja <archit@ti.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Move omapdrm device creation inside the omap_display_init so that we can
correctly create the device based on the presence of omapdss within the
platform.

For example, on a kernel image supporting multiple platforms, omap_init_drm
will create a omapdrm platform device on a AM33xx platform even though it
doesn't have a DSS block.

Originally worked on by Andy Gross.

Cc: Andy Gross <andygro@gmail.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

DMM exists on omap4+ platforms, these platforms are always expected to boot with
DT. Remove the current method of searching the dmm hwmod and building an
omap_device for dmm.

For OMAP4, the address and irq data for DMM hwmod(along with other blocks) were
removed, so the current method fails in the dmm driver's probe anyway.

The addition of DMM nodes in DT will ensure that a DMM device is built
correctly.

Cc: Andy Gross <andygro@gmail.com>
Signed-off-by: NArchit Taneja <archit@ti.com>
Acked-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Adding this driver as platform device and only for RX-51 until somebody test if
it working also on other OMAP3 HS devices and until there will be generic ARM
way to deal with SMC calls.
Signed-off-by: NPali Rohár <pali.rohar@gmail.com>
[tony@atomide.com: folded in the clock alias change]
Signed-off-by: NTony Lindgren <tony@atomide.com>

Closed and signed Nokia X-Loader bootloader stored in RX-51 nand does not set
IBE bit in ACTLR and starting kernel in non-secure mode. So direct write to
ACTLR by our kernel does not working and the code for ARM errata 430973 in
commit 7ce236fc that sets IBE bit is a noop.

In order to have workaround for ARM errata 430973 from non-secure world on
RX-51 we needs Secure Monitor Call to set IBE BIT in ACTLR.

This patch adds RX-51 specific secure support code and sets IBE bit in ACTLR
during board init code for ARM errata 430973 workaround.

Note that new function rx51_secure_dispatcher() differs from existing
omap_secure_dispatcher(). It calling omap_smc3() and param[0] is nargs+1.

ARM errata 430973 workaround is needed for thumb-2 ISA compiled userspace
binaries. Without this workaround thumb-2 binaries crashing. So with this
patch it is possible to recompile and run applications/binaries with thumb-2
ISA on RX-51.
Signed-off-by: NIvaylo Dimitrov <freemangordon@abv.bg>
Signed-off-by: NPali Rohár <pali.rohar@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Here is new version (v4) of omap secure part patch:

Other secure functions omap_smc1() and omap_smc2() calling instruction smc #0
but Nokia RX-51 board needs to call smc #1 for PPA access.
Signed-off-by: NIvaylo Dimitrov <freemangordon@abv.bg>
Signed-off-by: NPali Rohár <pali.rohar@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>