1. 12 10月, 2007 3 次提交
  2. 15 10月, 2007 4 次提交
    • T
      x86: force timer broadcast on late AMD C1E detection · 89039b37
      Thomas Gleixner 提交于
      The 64bit SMP bootup is slightly different to the 32bit one. It enables
      the boot CPU local APIC timer before all CPUs are brought up. Some AMD C1E
      systems have the C1E feature flag only set in the secondary CPU. Due to
      the early enable of the boot CPU local APIC timer the APIC timer is
      registered as a fully functional device. When we detect the wreckage during
      the bringup of the secondary CPU, we need to force the boot CPU into
      broadcast mode. 
      
      Check the C1E caused APIC timer disable, when the secondary APIC timer is
      initialized. If the boot CPU APIC timer was registered as a functional
      clock event device, then fix this up and utilize the
      CLOCK_EVT_NOTIFY_BROADCAST_FORCE mechanism to force the already
      registered boot CPU APIC timer into broadcast mode.
      
      Tested by force injecting the failure mode.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      89039b37
    • T
      x86: move local APIC timer init to the end of start_secondary() · 3ac508be
      Thomas Gleixner 提交于
      Preparatory patch for the AMD C1E wreckage fixup.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      3ac508be
    • D
      x86: fix missing include for vsyscall · b097976e
      Dave Jones 提交于
       > Maybe I just picked a bad time to try, but...
       > 
       > arch/x86/kernel/alternative.c: In function 'apply_alternatives':
       > arch/x86/kernel/alternative.c:191: error: 'VSYSCALL_START' undeclared (first use in this function)
       > arch/x86/kernel/alternative.c:191: error: (Each undeclared identifier is reported only once
       > arch/x86/kernel/alternative.c:191: error: for each function it appears in.)
       > arch/x86/kernel/alternative.c:191: error: 'VSYSCALL_END' undeclared (first use in this function)
       > make[1]: *** [arch/x86/kernel/alternative.o] Error 1
       > make: *** [arch/x86/kernel] Error 2
      
      Try this.
      
      Include missing header for vsyscall.
      Signed-off-by: NDave Jones <davej@redhat.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      b097976e
    • A
      long vs. unsigned long - low-hanging fruits in drivers · 64b33619
      Al Viro 提交于
      deal with signedness of the stuff passed to set_bit() et.al.
      Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      64b33619
  3. 14 10月, 2007 26 次提交
  4. 13 10月, 2007 7 次提交
    • J
      x86/pci/acpi: fix DMI const-ification fallout · 752097ce
      Jeff Garzik 提交于
      Fix DMI const-ification fallout that appeared when merging subsystem
      trees.
      Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      752097ce
    • N
      x86: fence oostores on 64-bit · df1bdc06
      Nick Piggin 提交于
      movnt* instructions are not strongly ordered with respect to other stores,
      so if we are to assume stores are strongly ordered in the rest of the 64
      bit code, we must fence these off (see similar examples in 32 bit code).
      
      [ The AMD memory ordering document seems to say that nontemporal stores can
        also pass earlier regular stores, so maybe we need sfences _before_
        movnt* everywhere too? ]
      Signed-off-by: NNick Piggin <npiggin@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      df1bdc06
    • R
      [MIPS] SMP: Fix use of cpumasks. · ece8a9e4
      Ralf Baechle 提交于
      Noticed by Nick Piggin <nickpiggin@yahoo.com.au>.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      ece8a9e4
    • R
      [MIPS] Revert "[MIPS] tlbex.c: Cleanup __init usage." · 6f1ca1d2
      Ralf Baechle 提交于
      This reverts commit aaf76a32.
      
      As requested by ranck Bui-Huu <fbuihuu@gmail.com>.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      6f1ca1d2
    • J
      PCI: X86: Introduce and enable PCI domain support · a79e4198
      Jeff Garzik 提交于
      * fix bug in pci_read() and pci_write() which prevented PCI domain
        support from working (hardcoded domain 0).
      
      * unconditionally enable CONFIG_PCI_DOMAINS
      
      * implement pci_domain_nr() and pci_proc_domain(), as required of
        all arches when CONFIG_PCI_DOMAINS is enabled.
      
      * store domain in struct pci_sysdata, as assigned by ACPI
      
      * support "pci=nodomains"
      Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
      Cc: Andi Kleen <ak@suse.de>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      a79e4198
    • G
      PCI: modify PCI bridge control ISA flag for clarity · 11949255
      Gary Hade 提交于
      Modify PCI Bridge Control ISA flag for clarity
      
      This patch changes PCI_BRIDGE_CTL_NO_ISA to PCI_BRIDGE_CTL_ISA
      and modifies it's clarifying comment and locations where used.
      The change reduces the chance of future confusion since it makes
      the set/unset meaning of the bit the same in both the bridge
      control register and bridge_ctl field of the pci_bus struct.
      Signed-off-by: NGary Hade <garyhade@us.ibm.com>
      Acked-by: NLinas Vepstas <linas@austin.ibm.com>
      Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      11949255
    • G
      PCI: use _CRS for PCI resource allocation · 62f420f8
      Gary Hade 提交于
      Use _CRS for PCI resource allocation
      
      This patch resolves an issue where incorrect PCI memory and i/o ranges
      are being assigned to hotplugged PCI devices on some IBM systems.  The
      resource mis-allocation not only makes the PCI device unuseable but
      often makes the entire system unuseable due to resulting machine checks.
      
      The hotplug capable PCI slots on the affected systems are not located
      under a standard P2P bridge but are instead located under PCI root
      bridges or subtractive decode P2P bridges.  For example, the IBM x3850
      contains 2 hotplug capable PCI-X slots and 4 hotplug capable PCIe slots
      with the PCI-X slots each located under a PCI root bridge and the PCIe
      slots each located under a subtractive decode P2P bridge.
      
      The current i386/x86_64 PCI resource allocation code does not use _CRS
      returned resource information.  No other resource information source is
      available for slots that are not below a standard P2P bridge so
      incorrect ranges are being allocated from e820 hole causing the bad
      result.
      
      This patch causes the kernel to use _CRS returned resource info.  It is
      roughly based on a change provided by Matthew Wilcox for the ia64 kernel
      in 2005.  Due to possible buggy BIOS factor and possible yet to be
      discovered kernel issues the function is disabled by default and can be
      enabled with pci=use_crs.
      Signed-off-by: NGary Hade <gary.hade@us.ibm.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      62f420f8