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  1. 27 5月, 2016 1 次提交
  3. 12 3月, 2016 1 次提交
  5. 01 3月, 2016 1 次提交
  7. 19 2月, 2016 3 次提交
  9. 11 2月, 2016 1 次提交
  11. 17 11月, 2015 3 次提交
  13. 04 11月, 2015 1 次提交
  15. 31 10月, 2015 1 次提交
  17. 25 8月, 2015 1 次提交
    • Z
      PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI · 91f15fb3
      由 Zhang Rui 提交于 
      On multi-function JMicron SATA/PATA/AHCI devices, the PATA controller at
function 1 doesn't work if it is powered on before the SATA controller at
function 0.  The result is that PATA doesn't work after resume, and we
print messages like this:

  pata_jmicron 0000:02:00.1: Refused to change power state, currently in D3
  irq 17: nobody cared (try booting with the "irqpoll" option)

Async resume was introduced in v3.15 by 76569faa ("PM / sleep:
Asynchronous threads for resume_noirq").  Prior to that, we powered on
the functions in order, so this problem shouldn't happen.

e6b7e41c ("ata: Disabling the async PM for JMicron chip 363/361")
solved the problem for JMicron 361 and 363 devices.  With async suspend
disabled, we always power on function 0 before function 1.

Barto then reported the same problem with a JMicron 368 (see comment #57 in
the bugzilla).

Rather than extending the blacklist piecemeal, disable async suspend for
all JMicron multi-function SATA/PATA/AHCI devices.

This quirk could stay in the ahci and pata_jmicron drivers, but it's likely
the problem will occur even if pata_jmicron isn't loaded until after the
suspend/resume.  Making it a PCI quirk ensures that we'll preserve the
power-on order even if the drivers aren't loaded.

[bhelgaas: changelog, limit to multi-function, limit to IDE/ATA]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=81551Reported-and-tested-by: NBarto <mister.freeman@laposte.net>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.15+
      91f15fb3
  19. 18 6月, 2015 1 次提交
  21. 17 6月, 2015 2 次提交
    • R
      ahci: Add support for Cavium's ThunderX host controller · b7ae128d
      由 Robert Richter 提交于 
      This patch adds support for Cavium's ThunderX host controller. The
controller resides on the SoC and is a AHCI compatible SATA controller
with one port, compliant with Serial ATA 3.1 and AHCI Revision 1.31.
There can exists multiple SATA controllers on the SoC.

The controller depends on MSI-X support since the PCI ECAM controller
on the SoC does not implement MSI nor lagacy intx interrupt support.
Thus, during device initialization, if MSI fails MSI-X will be used to
enable the device's interrupts.

The controller uses non-standard BAR0 for its register range. The
already existing device lookup (vendor and device id) that is already
implemented for other host controllers is used to change the PCI BAR.
Signed-off-by: NRobert Richter <rrichter@cavium.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      b7ae128d
    • R
      ahci: Add generic MSI-X support for single interrupts to SATA PCI driver · ee2aad42
      由 Robert Richter 提交于 
      This patch adds generic MSI-X support for single interrupts to the
SATA PCI driver. MSI-X support is needed for host controller that only
have MSI-X support implemented, but no MSI or intx. This patch only
adds support for single interrupts, multiple per-port MSI-X interrupts
are not yet implemented.

The new implementation still initializes MSIs first. Only if that
fails, the code tries to enable MSI-X. If that fails too, setup is
continued with intx interrupts.

To not break other chips by this generic code change, there are the
following precautions:

 * Interrupt ranges are not enabled at all.

 * Only single interrupt mode is enabled for msix cap devices. Thus,
   only one interrupt will be setup.

 * During the discussion with Tejun we agreed to change the init
   sequence from msix-msi-intx to msi-msix-intx. Thus, if a device
   offers msi and init does not fail, the msix init code will not be
   executed. This is equivalent to current code.

With this, the code only setups single mode msix as a last resort if
msi fails. No interrupt range is enabled at all. Only one interrupt
will be enabled.

tj: comment edits.

Changes of the patch series:

v5:
 * updated patch subject that the patch only implements single IRQ
 * moved Cavium specific code to a separate patch
 * detect Cavium ThunderX device with PCI_CLASS_STORAGE_SATA_AHCI
   instead of vendor/dev id
 * added more comments to the code
 * enable single msix support for all kind of devices (removing strict
   check)
 * rebased onto update libata/for-4.2 with patch 1, 2 applied

v4:
 * removed implementation of ahci_init_intx()
 * improved patch descriptions
 * rebased onto libata/for-4.2

v3:
 * store irq number in struct ahci_host_priv
 * change initialization order from msix-msi-intx to msi-msix-intx
 * improve comments in ahci_init_msix()
 * improve error message in ahci_init_msix()
 * do not enable MSI-X if MSI is actively disabled for the device

v2:
 * determine irq vector from pci_dev->msi_list

Based on a patch from Sunil Goutham <sgoutham@cavium.com>.
Signed-off-by: NRobert Richter <rrichter@cavium.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      ee2aad42
  23. 03 6月, 2015 2 次提交
    • R
      ahci: Store irq number in struct ahci_host_priv · 21bfd1aa
      由 Robert Richter 提交于 
      Currently, ahci supports only msi and intx. To also support msix the
handling of the irq number need to be changed. The irq number for msix
devices is taken from msi_list instead of pci_dev. Thus, the irq
number of a device needs to be stored in struct ahci_host_priv now.
This allows the host controller to be activated in a generic way.

This change is only intended for ahci drivers. For that reason the irq
number is stored in struct ahci_host_priv used only by ahci drivers.
Thus, the ABI changes only for ahci_host_activate(), but existing ata
drivers (about 50) are unaffected and keep unchanged. All users of
ahci_host_activate() have been updated.

While touching drivers/ata/libahci.c, doing a small code cleanup in
ahci_port_start().
Signed-off-by: NRobert Richter <rrichter@cavium.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      21bfd1aa
    • R
      ahci: Move interrupt enablement code to a separate function · a1c82311
      由 Robert Richter 提交于 
      This patch refactors ahci_init_interrupts() and moves msi code to a
separate function. Need the split since we add msix initialization in
a later patch. The initialization for msix will be done after msi but
before intx.
Signed-off-by: NRobert Richter <rrichter@cavium.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      a1c82311
  25. 10 5月, 2015 1 次提交
  27. 08 4月, 2015 1 次提交
    • Q
      ata: remove deprecated use of pci api · c54c719b
      由 Quentin Lambert 提交于 
      Replace occurences of the pci api by appropriate call to the dma api.

A simplified version of the semantic patch that finds this problem is as
follows: (http://coccinelle.lip6.fr)

@deprecated@
idexpression id;
position p;
@@

(
  pci_dma_supported@p ( id, ...)
|
  pci_alloc_consistent@p ( id, ...)
)

@bad1@
idexpression id;
position deprecated.p;
@@
...when != &id->dev
   when != pci_get_drvdata ( id )
   when != pci_enable_device ( id )
(
  pci_dma_supported@p ( id, ...)
|
  pci_alloc_consistent@p ( id, ...)
)

@depends on !bad1@
idexpression id;
expression direction;
position deprecated.p;
@@

(
- pci_dma_supported@p ( id,
+ dma_supported ( &id->dev,
...
+ , GFP_ATOMIC
  )
|
- pci_alloc_consistent@p ( id,
+ dma_alloc_coherent ( &id->dev,
...
+ , GFP_ATOMIC
  )
)
Signed-off-by: NQuentin Lambert <lambert.quentin@gmail.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      c54c719b
  29. 13 1月, 2015 1 次提交
  31. 05 12月, 2014 1 次提交
  33. 03 12月, 2014 1 次提交
  35. 05 11月, 2014 1 次提交
  37. 28 10月, 2014 2 次提交
  39. 06 10月, 2014 3 次提交
  41. 28 9月, 2014 1 次提交
  43. 06 9月, 2014 1 次提交
  45. 01 9月, 2014 1 次提交
    • C
      ata: Disabling the async PM for JMicron chip 363/361 · e6b7e41c
      由 Chuansheng Liu 提交于 
      After enabled the PM feature that supporting async noirq(76569faa
(PM / sleep: Asynchronous threads for resume_noirq)),
Jay hit the system resuming issue, that one of the JMicron controller
can not be powered up.

His device tree is like below:
             +-1c.4-[02]--+-00.0  JMicron Technology Corp. JMB363 SATA/IDE Controller
             |            \-00.1  JMicron Technology Corp. JMB363 SATA/IDE Controller

After investigation, we found the the Micron chip 363 included
one SATA controller(0000:02:00.0) and one PATA controller(0000:02:00.1),
these two controllers do not have parent-children relationship,
but the PATA controller only can be powered on after the SATA controller
has finished the powering on.

If we enabled the async noirq(), then the below error is hit during noirq
phase:
pata_jmicron 0000:02:00.1: Refused to change power state, currently in D3

Here for JMicron chip 363/361, we need forcedly to disable the async method.

Bug detail: https://bugzilla.kernel.org/show_bug.cgi?id=81551Reported-by: NJay <MyMailClone@t-online.de>
Signed-off-by: NChuansheng Liu <chuansheng.liu@intel.com>
Acked-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
      e6b7e41c
  47. 31 8月, 2014 1 次提交
  49. 28 8月, 2014 1 次提交
  51. 31 7月, 2014 1 次提交
  53. 19 7月, 2014 1 次提交
  55. 04 6月, 2014 1 次提交
  57. 27 5月, 2014 1 次提交
  59. 24 4月, 2014 1 次提交
  61. 19 4月, 2014 1 次提交
    • A
      ahci: Do not receive interrupts sent by dummy ports · 2cf532f5
      由 Alexander Gordeev 提交于 
      In multiple MSI mode all AHCI ports (including dummy) get assigned
separate MSI vectors and (as result of execution
pci_enable_msi_exact() function) separate IRQ numbers, (mapped to the
MSI vectors).

Therefore, although interrupts from dummy ports are not desired they
are still enabled. We do not request IRQs for dummy ports, but that
only means we do not assign AHCI-specific ISRs to corresponding IRQ
numbers.

As result, dummy port interrupts still could come and traverse all the
way from the PCI device to the kernel, causing unnecessary overhead.

This update disables IRQs for dummy ports and prevents the described
issue.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NTejun Heo <tj@kernel.org>
Tested-by: NDavid Milburn <dmilburn@redhat.com>
Cc: linux-ide@vger.kernel.org
Cc: stable@vger.kernel.org
Fixes: 5ca72c4f ("AHCI: Support multiple MSIs")
      2cf532f5