- 20 11月, 2014 2 次提交
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由 Stephen M. Cameron 提交于
The hardware needs little endian scatter gather addresses and lengths but we were not bothering to convert from cpu byte order as we should have been. On Intel, this is all just a bunch of no-ops macros, but it makes the code endian-clean(er). Signed-off-by: NDon Brace <don.brace@pmcs.com> Signed-off-by: NRobert Elliott <elliott@hp.com> Reviewed-by: NWebb Scales <webbnh@hp.com> Signed-off-by: NChristoph Hellwig <hch@lst.de>
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由 Stephen M. Cameron 提交于
We were allocating roughly double the amount of memory we should be due to ReportLUNdata and ExtendedReportLUNdata containing a non-zero sized array but adding extra memory to allocate as if the array were zero sized. Track the logical and physical sizes separately. Allocate the memory based on the specific data structure sizes. Signed-off-by: NDon Brace <don.brace@pmcs.com> Reviewed-by: NWebb Scales <webb.scales@hp.com> Signed-off-by: NChristoph Hellwig <hch@lst.de>
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- 02 6月, 2014 4 次提交
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由 Stephen M. Cameron 提交于
Make return value an int instead of an unsigned char so that we do not lose negative error return values. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Reviewed-by: NWebb Scales <webb.scales@hp.com> Reported-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NChristoph Hellwig <hch@lst.de>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Reviewed-by: NJoe Handzik <joseph.t.handzik@hp.com> Signed-off-by: NChristoph Hellwig <hch@lst.de>
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由 Stephen M. Cameron 提交于
No sense having 8 or 16 reply queues if you only have 4 cpus, and likewise no sense limiting to 8 reply queues if you have many more cpus. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Reviewed-by: NMike Miller <michael.miller@canonical.com> Reviewed-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NChristoph Hellwig <hch@lst.de>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Reviewed-by: NWebb Scales <webb.scales@hp.com> Signed-off-by: NChristoph Hellwig <hch@lst.de>
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- 16 3月, 2014 16 次提交
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由 Stephen M. Cameron 提交于
This allows exposing physical disks behind Smart Array controllers to the OS (if the controller has the right firmware and is in "hba" mode) Signed-off-by: NJoe Handzik <joseph.t.handzik@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
Do not expose drives that are undergoing a format immediately to the OS, instead wait until they are ready before bringing them online. This is so that logical drives created with "rapid parity initialization" do not get immediately kicked off the system for being unresponsive. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Scott Teel 提交于
Add controller-based data-at-rest encryption compatibility to ioaccel2 path (HP SSD Smart Path). Encryption feature requires driver to supply additional fields for encryption enable, tweak index, and data encryption key index in the ioaccel2 request structure. Encryption enable flag and data encryption key index come from raid_map data structure from raid offload command. During ioaccel2 submission, check device structure's raid map to see if encryption is enabled for the device. If so, call new function below. Add function set_encrypt_ioaccel2 to set encryption flag, data encryption key index, and calculate tweak value from request's logical block address. Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Scott Teel 提交于
Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Scott Teel 提交于
Underlying firmware cannot handle task abort on accelerated path (SSD Smart Path). Change abort requests for accelerated path commands to physical target reset. Send reset request on normal IO path. Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NMike Miller <michael.miller@canonical.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Scott Teel 提交于
Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NJoe Handzik <Joseph.T.Handzik@hp.com> Signed-off-by: NMike Miller <michael.miller@canonical.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Mike Miller 提交于
Signed-off-by: NMike Miller <michael.miller@canonical.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
For shared SAS configurations, hosts need to poll Smart Arrays periodically in order to be able to detect configuration changes such as logical drives being added or removed from remote hosts. A register on the controller indicates when such events have occurred, and the driver polls the register via a workqueue and kicks off a rescan of devices if such an event is detected. Additionally, changes to logical drive raid offload eligibility are autodetected in this way. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
This enables sending i/o's destined for RAID logical drives which can be serviced by a single physical disk down a different, faster i/o path directly to physical drives for certain logical volumes on SSDs bypassing the Smart Array RAID stack for a performance improvement. Signed-off-by: NMatt Gates <matthew.gates@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NMike Miller <michael.miller@canonical.com> Signed-off-by: NDon Brace <brace@beardog.cce.hp.com> Signed-off-by: NJoe Handzik <joseph.t.handzik@hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Matt Gates 提交于
For certain i/o's to certain devices (unmasked physical disks) we can bypass the RAID stack firmware and do the i/o to the device directly and it will be faster. Signed-off-by: NMatt Gates <matthew.gates@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Matt Gates 提交于
This is normally optional, but for SSD Smart Path support (in subsequent patches) it is required. Signed-off-by: NMatt Gates <matthew.gates@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Matt Gates 提交于
There is an extended report luns command which contains additional information about physical devices. In particular we need to get the physical device handle so we can use an alternate i/o path for fast physical devices like SSDs so we can speed up certain i/o's by bypassing the RAID stack code in the controller firmware. Signed-off-by: NMatt Gates <matthew.gates@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 20 12月, 2013 2 次提交
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由 Stephen M. Cameron 提交于
This used to be the default, but at some point the firmware guys changed the default and I failed to notice. Now to get unit attention notifications, you must twiddle a bit indicating you want them. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
The field contains more bits than just the one to indicate whether scsi prefetch should be turned on. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 10 5月, 2012 3 次提交
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由 Stephen M. Cameron 提交于
Dial back the aggressiveness of the controller lockup detection thread. Currently it will declare the controller to be locked up if it goes for 10 seconds with no interrupts and no change in the heartbeat register. Dial back this to 30 seconds with no heartbeat change, and also snoop the ioctl path and if a firmware flash command is detected, dial it back further to 4 minutes until the firmware flash command completes. The reason for this is that during the firmware flash operation, the controller apparently doesn't update the heartbeat register as frequently as it is supposed to, and we can get a false positive. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Matt Gates 提交于
Smart Arrays can support multiple reply queues onto which command completions may be deposited. It can help performance quite a bit to arrange for command completions to be processed on the same CPU from which they were submitted to increase the likelihood of cache hits. Signed-off-by: NMatt Gates <matthew.gates@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 19 2月, 2012 2 次提交
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由 Scott Teel 提交于
Driver limits SAS external target IDs to range 1-8. Need to increase limit and clean up overlapping concepts of targets and paths in the code. There are several defined constants that control this: HPSA_MAX_TARGETS_PER_CTLR 16 MAX_MSA2XXX_ENCLOSURES 32 HPSA_MAX_PATHS 8 We can condense this to one constant: MAX_EXT_TARGETS 32 SAS switches allow for 8 connections, and there is capacity for 4 switches per enclosure in largest blade enclosure type. Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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由 Stephen M. Cameron 提交于
[SCSI] hpsa: removed unneeded structure member max_sg_entries and fix badly named constant MAXSGENTRIES We had both h->max_sg_entries and h->maxsgentries in the per controller structure which is terribly confusing. max_sg_entries was really just a constant, 32, which defines how big the "block fetch table" is, which is as large as the max number of SG elements embedded within a command (excluding SG elements in chain blocks). MAXSGENTRIES was the constant used to denote the max number of SG elements embedded within a command, also a poor name. So renamed MAXSGENTREIS to SG_ENTRIES_IN_CMD, and removed h->max_sg_entries and replaced it with SG_ENTRIES_IN_CMD. h->maxsgentries is unchanged, and is the maximum number of sg elements the controller will support in a command, including those in chain blocks, minus 1 for the chain block pointer.. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 30 10月, 2011 1 次提交
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由 Scott Teel 提交于
The currentsd[] array in hpsa_update_scsi_devices had room for 256 devices. The code was iterating over however many physical and logical devices plus an additional number of possible external MSA2XXX controllers, which together could potentially exceed 256. We increased the size of the currentsd array to 1024 + 1024 + 32 + 1 elements to reflect a reasonable maximum possible number of devices which might be encountered. We also don't just walk off the end of the array if the array controller reports more devices than we are prepared to handle, we just ignore the excessive devices. Signed-off-by: NScott Teel <scott.teel@hp.com> Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <JBottomley@Parallels.com>
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- 17 5月, 2011 3 次提交
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由 Stephen M. Cameron 提交于
The bit-2-doorbell reset method seemed to cause (survivable) NMIs on some systems and (unsurvivable) IOCK NMIs on some G7 servers. Firmware guys implemented a new doorbell method to alleviate these problems triggered by bit 5 of the doorbell register. We want to use it if it's available. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <jbottomley@parallels.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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由 Stephen M. Cameron 提交于
Detect failure of controller reset by noticing if the 32 bytes of "driver version" we store on the hardware in the config table fail to get zeroed out. Previously we noticed if the controller did not transition to "simple mode", but this did not detect reset failure if the controller was already in simple mode prior to the reset attempt (e.g. due to module parameter hpsa_simple_mode=1). Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <jbottomley@parallels.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <jbottomley@parallels.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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- 19 2月, 2011 2 次提交
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由 Stephen M. Cameron 提交于
Controller will transfer only 32-bits on completion if it knows we are only using 32-bit tags. Also, some newer controllers apparently (and erroneously) require that we only use 32-bit tags, and that we inform the controller of this. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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由 Stephen M. Cameron 提交于
Driver's internal queues should be FIFO, not LIFO. This is a port of an almost identical patch from cciss by Jens Axboe. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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- 25 1月, 2011 1 次提交
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由 Stephen M. Cameron 提交于
Some low bits might have been set by the driver, causing a message like this to come out: [ 13.288062] ------------[ cut here ]------------ [ 13.293211] WARNING: at lib/dma-debug.c:803 check_unmap+0x1a1/0x654() [ 13.300387] Hardware name: ProLiant DL180 G6 [ 13.305335] hpsa 0000:06:00.0: DMA-API: device driver tries to free DMA memory it has not allocated [device address=0x000000007f81e001] [size=640 bytes] Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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- 28 7月, 2010 1 次提交
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由 Stephen M. Cameron 提交于
Smart Array controllers newer than the P600 do not honor the PCI power state method of resetting the controllers. Instead, in these cases we can get them to reset via the "doorbell" register. This escaped notice until we began using "performant" mode because the fact that the controllers did not reset did not normally impede subsequent operation, and so things generally appeared to "work". Once the performant mode code was added, if the controller does not reset, it remains in performant mode. The code immediately after the reset presumes the controller is in "simple" mode (which previously, it had remained in simple mode the whole time). If the controller remains in performant mode any code which presumes it is in simple mode will not work. So the reset needs to be fixed. Unfortunately there are some controllers which cannot be reset by either method. (eg. p800). We detect these cases by noticing that the controller seems to remain in performant mode even after a reset has been attempted. In those case, we proceed anyway, as if the reset has happened (and skip the step of waiting for the controller to become ready -- which is expecting it to be in "simple" mode.) To sum up, we try to do a better job of resetting the controller if "reset_devices" is set, and if it doesn't work, we print a message and try to continue anyway. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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- 02 5月, 2010 1 次提交
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由 Mike Miller 提交于
This patch removes unnecessary #define's from hpsa. The SCSI midlayer handles all this for us. Signed-off-by: NMike Miller <mike.miller@hp.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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- 03 3月, 2010 2 次提交
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由 Stephen M. Cameron 提交于
Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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由 Stephen M. Cameron 提交于
This uses the scatter-gather chaining feature of Smart Array controllers. 32 scatter-gather elements are embedded in the "command list", and the last element in the list may be marked as a "chain pointer", and point to an additional block of scatter gather elements. The precise number of scatter gather elements supported is dependent on the particular kind of Smart Array, and is determined at runtime by querying the hardware. Signed-off-by: NStephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: NJames Bottomley <James.Bottomley@suse.de>
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