Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

This change removes the interrupt resource. The driver does not use
it.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Changing eg 0xffffffff to DMA_BIT_MASK(32) etc allows easier
side by side comparision of identical code which can be consolidated.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Use irq_set_chip_and_handler() instead. Converted with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Convert to the new function names. Automated with coccinelle.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Remove the obsolete desc_handle_irq() helper.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

commit 9eac6d0a (ARM: Remove dependency of plat-orion GPIO code on mach
directory includes) missed to convert one instance of
DOVE_GPIO_VIRT_BASE and left the orion_gpio_init() in mpp.c

Fix it up.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Remove call to the old GPIO init function.
Fix old MPP control offset value.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Acked-by: NSaeed Bishara <saeed.bishara@gmail.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

These are not currently used anywhere, but when the relevant
peripherals are enabled on the Dove port, the IRQ numbers should be
passed into the drivers via platform device resources rather than
having the drivers get them from platform headers directly.
Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Acked-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

This patch makes the various mach dirs that use the plat-orion GPIO
code pass in GPIO-related platform info (GPIO controller base address,
secondary base IRQ number, etc) explicitly, instead of having
plat-orion get those values by including a mach dir include file --
the latter mechanism is problematic if you want to support multiple
ARM platforms in the same kernel image.
Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

This patch makes the various mach dirs that use the plat-orion time
code pass in timer and bridge addresses explicitly, instead of having
plat-orion get those values by including a mach dir include file --
the latter mechanism is problematic if you want to support multiple
ARM platforms in the same kernel image.
Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

This uncouple PHYS_OFFSET from the platform definitions, thereby
facilitating run-time computation of the physical memory offset.
Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NMagnus Damm <damm@opensource.se>
Acked-by: NTony Lindgren <tony@atomide.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NWan ZongShun <mcuos.com@gmail.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Acked-by: NEric Miao <eric.y.miao@gmail.com>
Acked-by: NJiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Make Dove platforms select the new V6K CPU option.
Tested-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca>
Acked-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
CC: Saeed Bishara <saeed@marvell.com>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NChris Ball <cjb@laptop.org>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Acked-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Acked-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

This patch adds support for CM-A510 machine
Signed-off-by: NKonstantin Sinyuk <kostyas@compulab.co.il>
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Reviewed-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Since we're now using addruart to establish the debug mapping, we can
remove the io_pg_offst and phys_io members of struct machine_desc.

The various declarations were removed using the following script:

  grep -rl MACHINE_START arch/arm | xargs \
  sed -i '/MACHINE_START/,/MACHINE_END/ { /\.\(phys_io\|io_pg_offst\)/d }'

[ Initial patch was from Jeremy Kerr, example script from Russell King ]
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Eric Miao <eric.miao at canonical.com>

Rather than checking the MMU status in every instance of addruart, do it
once in kernel/debug.S, and change the existing addruart macros to
return both physical and virtual addresses. The main debug code can then
select the appropriate address to use.

This will also allow us to retreive the address of a uart for the MMU
state that we're not current in.

Updated with fixes for OMAP from Jason Wang <jason77.wang@gmail.com>
and Tony Lindgren <tony@atomide.com>, and fix for versatile express from
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>.
Signed-off-by: NJeremy Kerr <jeremy.kerr@canonical.com>
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NJason Wang <jason77.wang@gmail.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Tested-by: NKevin Hilman <khilman@deeprootsystems.com>

Signed-off-by: NEric Miao <eric.miao@canonical.com>
Acked-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@fluxnic.net>

Makes it consistent with VMALLOC_START
Tested-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NAndreas Fenkart <andreas.fenkart@streamunlimited.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Otherwise more complicated uart configuration won't be possible.
We can use r1 for tmp register for both head.S and debug.S.

NOTE: This patch depends on another patch to add the the tmp register
into all debug-macro.S files. That can be done with:

$ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/"
	arch/arm/*/include/*/debug-macro.S
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The (void *) cast is not needed when setting dev.platform_data to the
address of the data. Remove the casts.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Support for the Tauros2 L2 cache controller as used with the PJ1
and PJ4 CPUs.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

The Marvell Dove (88AP510) is a high-performance, highly integrated,
low power SoC with high-end ARM-compatible processor (known as PJ4),
graphics processing unit, high-definition video decoding acceleration
hardware, and a broad range of peripherals.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
Signed-off-by: NSaeed Bishara <saeed@marvell.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>