- 20 9月, 2012 18 次提交
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由 Lee Jones 提交于
This patch removes platform device registration of all 4 MSP devices. It also takes care of all redundant infrastructure now that each of the ux500 audio components have been Device Tree enabled. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
In this patch we prevent MOP500 driver registration from platform code and rely solely on Device Tree to do the probing for us. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
It isn't currently possible to pass all platform specific configuration though Device Tree. Thinks like device names used in the clock infrastructure, call-backs and DMA information have to be passed in via AUXDATA structures and the MSP is no exception. Here we're passing DMA settings. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
We've done this before and it worked well last time. Here we're duplicating a complex registration function to ease the process of enabling it for Device Tree. As there are quite a few steps taken during the registration process, it makes sense to break them up into more manageable chunks. This patch will aid us. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
Ensure correct probing and pass though important configuration options to the AB8500 CODEC driver when DT is enabled Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
This patch contains a couple of general MSP clean-ups pertaining to layout changes and changing functions to be void instead of int instead of regardlessly returning '0'. Acked-by: NOla Lilja <ola.o.lilja@stericsson.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
There are four SDIs on the HREF, as opposed to the original two enabled on Snowball. To get them working we have to pass their DMA information in the same was as we need with the other two. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
Here we add three nodes enabling UART support on the HREF hardware reference board. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
First commit applying the new Device Tree for ST-Ericsson's u8500 based hardware reference board. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
Since initial support was provided for the Nomadik I2C driver, it has been converted to an AMBA device. AMBA devices are probed in a slightly different way to other devices, so we have to identify them using an "arm,primecell" compatible string. As well as doing just that, this patch specifies which regulators the controller should use and requests a clock-speed. The latter is provided as more of an example, as it's the same as the recently changed default configuration. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
The compatible string found in the Power-On-Key's MFD cell matches the device name provided in the driver. Keeping this naming convention seems like a good idea, so we're changing the one found in the DTS file to match. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
This was left over during a recent clean-up which removed Device Tree helper structs. There is no longer a requirement for it, so we can just remove it. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
It's understood that the AB8500 should be subordinate to the DB8500; however, the AB8500 uses the GIC as it's interrupt controller. If we do not specify which IRQ controller to use the default is to use the next encountered IRQ controller as we climb the tree. This would be the DB8500. This patch ensures the AB8500 makes use of the correct interrupt controller. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
We're just about to provide the DB8500-PRCMU with its own IRQ domain, so that its subordinate drivers can use it as an interrupt controller. It's obligatory for all IRQ controllers to reference themselves as such from its own node in Device Tree. This patch does just that. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
When booting with Device Tree we need a way to call-back to the DB8500 PMU IRQ handler. This is necessary because the two CPU IRQ lines are muxed together on the DB8500 chip. The DB8500 PMU IRQ handler contains logic to pass over to the other core in the case of IRQ_NONE. This patch allows the DB8500 PMU IRQ handler to be passed to Perf through platform data. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
Here we remove some of the extra overhead we introduced to make DT:ing the Snowball platform easier. Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Lee Jones 提交于
In the initial submission of the MSP driver msp1 and msp3's associated pinctrl mechanism was passed back to platform code using a plat_init() call-back routine, but it has no place in platform code. The MSP driver should set this up for the appropriate ports. Instead we use a use_pinctrl identifier which is passed from platform_data/Device Tree which indicates which ports should use pinctrl. Acked-by: NOla Lilja <ola.o.lilja@stericsson.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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- 11 9月, 2012 2 次提交
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由 Fabio Estevam 提交于
SSI block has two types of clock: ipg: bus clock, the clock needed for accessing registers. per: peripheral clock, the clock needed for generating the bit rate. Currently SSI driver only supports slave mode and only need to handle the ipg clock, because the peripheral clock comes from the master codec. Only register the ipg clock and do not register the peripheral clock for ssi. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Tested-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Cc: stable@vger.kernel.org
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由 Fabio Estevam 提交于
SSI block has two types of clock: ipg: bus clock, the clock needed for accessing registers. per: peripheral clock, the clock needed for generating the bit rate. Currently SSI driver only supports slave mode and only need to handle the ipg clock, because the peripheral clock comes from the master codec. Only register the ipg clock and do not register the peripheral clock for ssi. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Cc: stable@vger.kernel.org
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- 10 9月, 2012 4 次提交
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由 Thomas Petazzoni 提交于
The __free_from_pool() function was changed in e9da6e99. Unfortunately, the test that checks whether the provided (start,size) is within the DMA pool has been improperly modified. It used to be: if (start < coherent_head.vm_start || end > coherent_head.vm_end) Where coherent_head.vm_end was non-inclusive (i.e, it did not include the first byte after the pool). The test has been changed to: if (start < pool->vaddr || start > pool->vaddr + pool->size) So now pool->vaddr + pool->size is inclusive (i.e, it includes the first byte after the pool), so the test should be >= instead of >. This bug causes the following message when freeing the *first* DMA coherent buffer that has been allocated, because its virtual address is exactly equal to pool->vaddr + pool->size : WARNING: at /home/thomas/projets/linux-2.6/arch/arm/mm/dma-mapping.c:463 __free_from_pool+0xa4/0xc0() freeing wrong coherent size from pool Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Lior Amsalem <alior@marvell.com> Cc: Maen Suleiman <maen@marvell.com> Cc: Tawfik Bayouk <tawfik@marvell.com> Cc: Shadi Ammouri <shadi@marvell.com> Cc: Eran Ben-Avi <benavi@marvell.com> Cc: Yehuda Yitschak <yehuday@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> [m.szyprowski: rebased onto v3.6-rc5 and resolved conflict] Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
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由 Will Deacon 提交于
The delay functions may be called by some platforms between switching to the timer-based delay loop but before calibration. In this case, the initial loops_per_jiffy may not be suitable for the timer (although a compromise may be achievable) and delay times may be considered too inaccurate. This patch updates loops_per_jiffy when switching to the timer-based delay loop so that delays are consistent prior to calibration. Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
The user access functions may generate a fault, resulting in invocation of a handler that may sleep. This patch annotates the accessors with might_fault() so that we print a warning if they are invoked from atomic context and help lockdep keep track of mmap_sem. Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
The {get,put}_user macros don't perform range checking on the provided __user address when !CPU_HAS_DOMAINS. This patch reworks the out-of-line assembly accessors to check the user address against a specified limit, returning -EFAULT if is is out of range. [will: changed get_user register allocation to match put_user] [rmk: fixed building on older ARM architectures] Reported-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Cc: stable@vger.kernel.org Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 08 9月, 2012 4 次提交
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由 Will Deacon 提交于
get_user may fail to load from the provided __user address due to an unhandled fault generated by the access. In the case of the undefined instruction trap, this results in failure to load the faulting instruction, in which case we should send SIGILL to the task rather than continue with potentially uninitialised data. Signed-off-by: NWill Deacon <will.deacon@arm.com> Cc: stable@vger.kernel.org Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Stephen Boyd 提交于
It seems we were missing some text in the title for the semihosting DEBUG_LL option. Add in the "/O" and fix up some minor typos in the help text. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 David Brown 提交于
'make dtbs' in a clean tree will try running the dtc before actually building it. Make these rules depend upon the scripts to build it. Cc: <stable@vger.kernel.org> Signed-off-by: NDavid Brown <davidb@codeaurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Stephen Boyd 提交于
During the p2v changes, the PHYS_OFFSET #define moved into a !__ASSEMBLY__ section. This causes a XIP build to fail with arch/arm/kernel/head.o: In function 'stext': arch/arm/kernel/head.S:146: undefined reference to 'PHYS_OFFSET' Momentarily leave the #ifndef __ASSEMBLY__ section so we can define PHYS_OFFSET for all compilation units. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 05 9月, 2012 2 次提交
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由 Linus Walleij 提交于
Test-compiling obscure machines I notice that the gemini (which by the way lacks a defconfig) is broken since some time back. Adding a simple missing include makes it build again. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NOlof Johansson <olof@lixom.net>
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由 Tony Lindgren 提交于
If NR_IRQS is less than MAX_IRQS, we end up writing past the irq_target_cpu array in omap_wakeupgen_init(): /* Associate all the IRQs to boot CPU like GIC init does. */ for (i = 0; i < max_irqs; i++) irq_target_cpu[i] = boot_cpu; This can happen if SPARSE_IRQ is enabled as by default NR_IRQS is set to 16. Without this patch we're overwriting other data during the boot. Looks like a similar fix was posted by Benoit Cousson earlier as "ARM: OMAP2+: wakeupgen: Fix wrong array size for irq_target_cpu" but was lost. Cc: stable@vger.kernel.org Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 04 9月, 2012 5 次提交
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由 Tero Kristo 提交于
The OMAP4 sl2if IP block requires some special programming for it to enter idle. Without this programming, it will prevent the rest of the chip from entering full chip idle. This patch comments out the IP block data. Later, once the appropriate support is available, this patch can be reverted. Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Misael Lopez Cruz 提交于
Clock and module mode are explictly enable when hwmod is enabled. But if the hwmod doesn't get ready on time, clocks are disabled but module is left enabled. Signed-off-by: NMisael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: NRajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Tero Kristo 提交于
IVA2 hwmod resets were missing the status bit offsets. Also, as the hwmod itself didn't have prcm info at all, resetting iva hwmod was accessing some bogus memory addresses. Added both infos to fix this. Signed-off-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
Commit 4da71ae6 ("OMAP: clockdomain: Arch specific funcs for clkdm_clk_enable/disable") called the OMAP2xxx-specific functions for clockdomain wakeup and sleep. This would probably have broken software-supervised clockdomain wakeup and sleep on OMAP3. Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Jon Hunter <jon-hunter@ti.com> Acked-by: NRajendra Nayak <rnayak@ti.com>
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由 Vaibhav Hiremath 提交于
With commit ae6df418 Sub: ARM: OMAP2+: dmtimer: cleanup fclk usage) The Timer functional clock naming convention has changed from gptX_fck => timerXfck, and so as the timer init function in mach-omap2/timer.c. OMAP4 clocktree also has changed accordingly. AM33xx Clock Tree has been merged during rc3-4 timeframe, before above commit got merged, so similar change is required for AM33xx as well (Change the gptX_fck => timerX_fck). Signed-off-by: NVaibhav Hiremath <hvaibhav@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 03 9月, 2012 1 次提交
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由 Kuninori Morimoto 提交于
armadillo800eva default boot loader is "hermit", and it's tag->u.core.flags has flag when kernel boots. Because of this, ${LINUX}/arch/arm/kernel/setup.c :: parse_tag_core() didn't remove MS_RDONLY flag from root_mountflags. Thus, the rootfs is mounted as "readonly". This patch adds "rw" kernel parameter, and enable read/write mounts for rootfs Cc: Masahiro Nakai <nakai@atmark-techno.com> Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms@verge.net.au>
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- 31 8月, 2012 4 次提交
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由 Andrew Lunn 提交于
Linux-next has failed to compile for kirkwood since 23 August with: arch/arm/mach-kirkwood/db88f6281-bp-setup.c:29: error: 'SZ_1M' undeclared here (not in a function) arch/arm/mach-kirkwood/db88f6281-bp-setup.c:33: error: 'SZ_4M' undeclared here (not in a function) Add missing <linux/sizes.h> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Kuninori Morimoto 提交于
renesas_usbhs driver can play role as both Host and Gadget. In case of Gadget, it requires not only renesas_usbhs but also usb gadget module (like g_ether). So, renesas_usbhs driver calls usb_add_gadget_udc() on probe time. Because of this behavior, Host port plays also Gadget role if kernel has both Host/Gadget support. In mackerel case, from 0ada2da5 (ARM: mach-shmobile: mackerel: use renesas_usbhs instead of r8a66597_hcd) usb0 plays Gadget role, and usb1 plays Host role, and current mackerel board probes as usb1 -> usb0. Thus, 1st installed usb gadget module (like g_ether) will be assigned to usb1 (= usb Host port), and 2nd module to usb0 (= usb Gadget port). It is very confusable for user. This patch fixup usb modes probing order as usb0 -> usb1. Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms@verge.net.au>
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由 Kuninori Morimoto 提交于
Since armadillo800eva has 2 sound cards, and had reversed deferred probe order issue, it was purposely registered in reverse order. But it was solved by 1d29cfa5 (driver core: fixup reversed deferred probe order) armadillo800eva board is expecting that FSI-WM8978 is the 1st, and FSI-HDMI is the 2nd sound card. This patch fixes it up Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms@verge.net.au>
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由 Radek Pilar 提交于
Fix inconsistency between mach-types and CONFIG_ name that prevents touchbook board from booting. Signed-off-by: NRadek Pilar <mrkva@mrkva.eu> Signed-off-by: NTony Lindgren <tony@atomide.com>
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