Also add label for backlight_lvds and connect it to the LVDS display.
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The DAI mode is and should be configured by the sound card driver as
codec and ssi have to be in the right modes to communicate with each
other. It is possible to operate the ssi unit or the codec in master mode,
sometimes even on the same board in different configurations.

With the latest changes in the fsl-ssi driver, the 'fsl,mode' property
is only handled as a fallback property. If the sound card sets the DAI
mode correctly, this fallback configuration is dropped.
Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This adds the stdout-path property to various i.MX boards. Values
of the property have been taken from barebox, so they should be
correct. Also, the older linux,stdout-path property is converted
to stdout-path.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This works around a hardware bug.
From "Chip Errata for the i.MX 6Dual/6Quad"

ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
system from Wait mode.

The ENET block generates many interrupts. Only one of these interrupt lines
is connected to the General Power Controller (GPC) block, but a logical OR
of all of the ENET interrupts is connected to the General Interrupt Controller
(GIC). When the system enters Wait mode, a normal RX Done or TX Done does not
wake up the system because the GPC cannot see this interrupt. This impacts
performance of the ENET block because its interrupts are serviced only when
the chip exits Wait mode due to an interrupt from some other wake-up source.

Before this patch, ping times of a Sabre Lite board are quite
random:
ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=15.7 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=14.4 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=13.4 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=12.4 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=11.4 ms

=== 192.168.0.13 ping statistics ===
5 packets transmitted, 5 received, 0% packet loss, time 2004ms
rtt min/avg/max/mdev = 11.431/13.501/15.746/1.508 ms
____________________________________________________
After this patch:

ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=0.120 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=0.175 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=0.169 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=0.168 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=0.172 ms

=== 192.168.0.13 ping statistics ===
5 packets transmitted, 5 received, 0% packet loss, time 1999ms
rtt min/avg/max/mdev = 0.120/0.160/0.175/0.026 ms
____________________________________________________

Also, apply same change to imx6qdl-nitrogen6x.

This change may not be appropriate for all boards.
Sabre Lite uses GPIO6 as a power down output for a ov5642
camera. As this expansion board does not yet work with mainline,
this is not yet a conflict. It would be nice to have an alternative
fix for boards where this is a problem.

For example Sabre SD uses GPIO6 for I2C3_SDA. It also
has long ping times currently. But cannot use this fix
without giving up a touchscreen.

Its ping times are also random.

ping 192.168.0.19 -i.5 -c5
PING 192.168.0.19 (192.168.0.19) 56(84) bytes of data.
64 bytes from 192.168.0.19: icmp_req=1 ttl=64 time=16.0 ms
64 bytes from 192.168.0.19: icmp_req=2 ttl=64 time=15.4 ms
64 bytes from 192.168.0.19: icmp_req=3 ttl=64 time=14.4 ms
64 bytes from 192.168.0.19: icmp_req=4 ttl=64 time=13.4 ms
64 bytes from 192.168.0.19: icmp_req=5 ttl=64 time=12.4 ms

=== 192.168.0.19 ping statistics ---
5 packets transmitted, 5 received, 0% packet loss, time 2003ms
rtt min/avg/max/mdev = 12.451/14.369/16.057/1.316 ms
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Note that the fec driver code currently hard-codes an active-low
reset, regardless of the flags in the device tree.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add power, menu, home, back, volume up, and volume down
buttons.

Also, apply same changes to imx6qdl-nitrogen6x.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

KEY_COL4 is over-current for usbotg on Sabre Lite.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

GPIO16 is used for I2C3, not ENET_REF_CLK.
Also, remove pull-ups from tx pins, and ENET_MDIO
which has an external pull-up.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Set the data delays to min, and clock delays to max
because the traces are equal length on pcb.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

add pwm1 for lcd backlight
add pwm4 for lvds backlight
add pwm3 for ov5640 mipi clock
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Explicitly sets the pad GPIO_0 (sys_mclk) to 0x030b0.

Before this patch, it has the value 0x130b0 if using mainline u-boot.
So this patch also removes hysteresis. The 100k pulldown remains so
that a disabled clock will be low.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch moves pin EIM_D23 (phy reset) from pinctrl_hog to pinctrl_enet.
It also explicitly sets the pad to 0x000b0.

Before this patch, it has the value 0x1b0b0 if using mainline u-boot.
So this patch also removes hysteresis and a 100K pullup since the pad
is always an output.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch moves pin EIM_D22(power enable) from pinctrl_hog to pinctrl_usbotg.
It also explicitly sets the pad to 0x000b0, which is also the value
that it has before this patch if using mainline u-boot.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch moves pin EIM_D19 (CS) from pinctrl_hog to pinctrl_ecspi1.
It also explicitly sets the pad to 0x000b1.

Before this patch, it has the value 0x100b1 if using mainline u-boot.
So this patch also removes hysteresis since the pad is always an output.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch moves pin SD3_DAT5/4 (CD/WP) from pinctrl_hog to pinctrl_usdhc3.
It also explicitly sets the pad SD3_DAT5 to 0x1b0b0, which is also the value
that it has before this patch if using mainline u-boot.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch moves pin NANDF_D6 (CD) from pinctrl_hog to pinctrl_usdhc4.
It also explicitly sets the pad to 0x1b0b0, which is also the value
that it has before this patch if using mainline u-boot.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

On Sabre Lite usdhc4 is a micro sd slot, which has no
write protect.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Uart1 is available on Sabre Lite.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This makes the structure of Sabre Lite board files the same
as Sabre SD board files so that they are easier to compare.

By this, I mean that the majority of the file imx6q-sabrelite.dts
is moved to imx6qdl-sabrelite.dtsi so that both imx6q-sabrelite.dts
and imx6dl-sabrelite.dts can include it.

Now Sabre Lite has support for Dual Lite/Solo
processors.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

In order to follow the standard approach used on other imx dts files, place the
'status' node as the last one.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

We must specify the value of audmux pinctrl if we want to use pinctrl_pm().
Thus change bypass value 0x80000000 to what we exactly need.

This patch also seperately unset PUE bit for TXD so that IOMUX won't pull
up/down the pin after turning into tristate. When we use SSI normal mode to
playback monaural audio via I2S signal, there'd be a pulled curve occur to
its signal at the second slot if setting PUE bit for TXD. And it will make
the second channel to play a constant noise. So by keeping the signal level
in the second slot, we can get a constant high level signal (-1) or a low
level one (0).
Signed-off-by: NNicolin Chen <b42378@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

MX6QDL_PAD_EIM_D23__GPIO3_IO23 appears twice in the hog pin group.

Remove one of the occurrences.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The device tree specification recommends that generic name should be
used for nodes.  So instead of naming those fixed regulator nodes
arbitrarily, let's use the generic name 'regulator@num' for those nodes.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that
boards that share the same pinctrl setting do not have to define it time
and time again in <board>.dts.  However, along with the devices and use
cases being added continuously, the pinctrl setting nodes under iomuxc
becomes more than expected.  This bloats device tree blob for particular
board unnecessarily since only a small subset of those pinctrl setting
nodes will be used by the board.  It impacts not only the DTB file size
but also the run-time device tree lookup efficiency.

The patch moves all the pinctrl data into individual boards as needed.
With the changes, the pinctrl setting nodes becomes local to particular
board, and it makes no sense to continue numbering the setting for
given peripheral.  Thus, all the pinctrl phandler name gets updated to
have only peripheral name in there.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

MX6QDL_PAD_EIM_D23__GPIO3_IO23 pin is used to reset the ethernet phy.

Add it to the 'hog' group.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

imx6q-sabrelite board can be connected to a 1024x768 Hannstar LVDS panel.

Add support for it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Put the nodes in alphabetical order so that further node additions can be better
organized.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The CLKO is widely used by imx6q board designs to clock audio codec.
Since most codecs accept 24 MHz frequency, let's initially set up CLKO
with OSC24M (cko <-- cko2 <-- osc).  Then those board specific CLKO
setup for audio codec can be removed.

The board dts files also need an update on cko reference in codec node.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Only imx6q has the ahci sata controller, enable
it on imx6q platforms.
Signed-off-by: NRichard Zhu <r65037@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The imx6q and imx6dl are two pin-to-pin compatible SoCs.  The same board
design can work with either chip plugged into the socket, e.g. sabresd
and sabreauto boards.

We currently define pin groups in imx6q.dtsi and imx6dl.dtsi
respectively because the pad macro names are different between two
chips.  This brings a maintenance burden on having the same label point
to the same pin group defined in two places.

The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs
pad macro names.  Then the pin groups becomes completely common between
imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the
long term maintenance of imx6q/dt pin settings becomes easier.

Unfortunately, the change brings some dramatic diff stat, but it's all
about DTS file, and the ultimate net diff stat is good.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Currently, all imx pinctrl drivers maintain a big array of struct
imx_pin_reg which hard-codes data like register offset and mux mode
setting for each pin function.  Every time a new imx SoC support is
added, we need to add such a big mount of data.  With moving to single
kernel build, it's only matter of time to be blamed on memory consuming.

With DTC pre-processor support in place, the patch moves all these data
into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and
changing the PIN_FUNC_ID parsing code a little bit.

The pin id gets re-numbered based on mux register offset, or config
register offset if the pin has no mux register, so that kernel can
identify the pin id from register offsets provided by device tree.

As a bonus point of the change, those arbitrary magic numbers standing
for particular PIN_FUNC_ID in device tree sources are now replaced by
macros to improve the readability of dts files.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NDong Aisheng <dong.aisheng@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Replace /include/ (dtc) with #include (C pre-processor) for all imx DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.

This allows future use of #defines and header files in order to define
names for various constants, such as pinctrl settings. Use of those
features will increase the readability of the device tree files.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add dtsi for imx6q and imx6dl with non-common blocks moved into there.
Major differences between imx6dl and imx6q:

 * Dual vs. Quad cores
 * single vs. dual IPU
 * 128 vs. 256 KB OCRAM
 * imx6q: ECSPI5, OpenVG (GC355), SATA
 * imx6dl: I2C4, PXP, EPDC, LCDIF
 * iomuxc/pads definition
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

i.MX6 Quad and i.MX6 DualLite is similar enough to share one dtsi
file, so rename imx6q.dtsi to imx6qdl.dtsi preparing for the addition
of imx6dl support.

Another member of i.MX6 series i.MX6 SoloLite is different enough
from the other two, so it will stand as a separate dtsi.  That's why
we rename to imx6qdl.dtsi not imx6.dtsi.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Following omap3-evm.dts way, it changes all imx dts files to use label
in board dts to refer to nodes defined by soc dtsi.  Thus, the board
dts files become easier to read and edit with the least indentation
levels.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NRichard Zhao <richard.zhao@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>