Skip to content

R
raspberrypi-kernel

openeuler / raspberrypi-kernel

通知 13
Star 1
Fork 0
R
raspberrypi-kernel
切换分支/标签
  1. 08 6月, 2016 1 次提交
  3. 04 5月, 2016 1 次提交
  5. 01 4月, 2016 1 次提交
  7. 15 3月, 2016 1 次提交
  9. 10 3月, 2016 2 次提交
  11. 09 3月, 2016 3 次提交
  13. 06 3月, 2016 1 次提交
  15. 05 3月, 2016 1 次提交
  17. 18 2月, 2016 1 次提交
  19. 16 2月, 2016 1 次提交
  21. 15 2月, 2016 2 次提交
  23. 09 2月, 2016 1 次提交
  25. 07 7月, 2015 1 次提交
  27. 27 3月, 2015 2 次提交
    • J
      spi/rockchip: Add device tree property to configure Rx Sample Delay · 76b17e6e
      由 Julius Werner 提交于 
      We have found that we can sometimes see read failures on boards with
high-capacitance SPI lines. It seems that the controller samples the Rx
data line too early, and its register interface has an "Rx Sample Delay"
setting to fine-tune against this issue.

This patch adds a new optional device tree entry that can configure this
delay in terms of nanoseconds. The kernel will calculate the
best-fitting amount of parent clock ticks to program the controller with
based on that.
Signed-off-by: NJulius Werner <jwerner@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      76b17e6e
    • J
      spi/rockchip: Round up clock rate divisor to err on the safe side · 754ec43c
      由 Julius Werner 提交于 
      The Rockchip SPI driver currently calculates its clock rate divisor by
integer dividing the parent rate by the target rate, and then rounding
the result up to the next even number (since the divisor must be
even).

Clock rate divisors should always be rounded up, so that the resulting
frequency is lower or equal to the target. This is correctly done in the
second step here but not in the first, so we still have a risk of
exceeding the desired target frequency (e.g. setting spi-max-frequency
to 40000000 with a parent clock of 99000000 could lead to a divisor of
99000000 / 40000000 == 2 (which is even) that then results in an
effective frequency of 99000000 / 2 == 49500000 (potentially exceeding
the flash chip's specifications).

This patch changes the division to round up to fix this problem.
Signed-off-by: NJulius Werner <jwerner@chromium.org>
Signed-off-by: NMark Brown <broonie@kernel.org>
      754ec43c
  29. 07 3月, 2015 1 次提交
  31. 29 1月, 2015 1 次提交
    • A
      spi/rockchip: avoid uninitialized-use warning · 97cf5669
      由 Arnd Bergmann 提交于 
      We currently get a warning about potentially uninitialized variables
in the rockchip spi driver, at least in certain toolchain versions:

spi/spi-rockchip.c: In function 'rockchip_spi_prepare_dma':
include/linux/dmaengine.h:796:2: warning: 'txdesc' may be used uninitialized in this function
include/linux/dmaengine.h:796:2: warning: 'rxdesc' may be used uninitialized in this function

The reason seems to be that gcc cannot know whether the value
of the rs->rx and rs->tx variables change between the two points
these are accessed.

The code is actually correct, but to make this clearer to the
compiler, this changes the conditionals to test for the local
rxdesc/txdesc variables instead, which it knows won't change.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMark Brown <broonie@kernel.org>
      97cf5669
  33. 13 12月, 2014 1 次提交
  35. 12 11月, 2014 1 次提交
  37. 20 10月, 2014 1 次提交
  39. 17 10月, 2014 1 次提交
  41. 15 10月, 2014 2 次提交
  43. 25 9月, 2014 1 次提交
  45. 05 9月, 2014 2 次提交
  47. 29 8月, 2014 1 次提交
  49. 20 8月, 2014 1 次提交
  51. 26 7月, 2014 3 次提交
  53. 11 7月, 2014 4 次提交
  55. 05 7月, 2014 1 次提交
    • A
      spi/rockchip: add driver for Rockchip RK3xxx SoCs integrated SPI · 64e36824
      由 addy ke 提交于 
      In order to facilitate understanding, rockchip SPI controller IP design
looks similar in its registers to designware. But IC implementation
is different from designware, So we need a dedicated driver for Rockchip
RK3XXX SoCs integrated SPI. The main differences:

- dma request line: rockchip SPI controller have two DMA request line
  for tx and rx.

- Register offset:
                  RK3288        dw
  SPI_CTRLR0      0x0000        0x0000
  SPI_CTRLR1      0x0004        0x0004
  SPI_SSIENR      0x0008        0x0008
  SPI_MWCR        NONE          0x000c
  SPI_SER         0x000c        0x0010
  SPI_BAUDR       0x0010        0x0014
  SPI_TXFTLR      0x0014        0x0018
  SPI_RXFTLR      0x0018        0x001c
  SPI_TXFLR       0x001c        0x0020
  SPI_RXFLR       0x0020        0x0024
  SPI_SR          0x0024        0x0028
  SPI_IPR         0x0028        NONE
  SPI_IMR         0x002c        0x002c
  SPI_ISR         0x0030        0x0030
  SPI_RISR        0x0034        0x0034
  SPI_TXOICR      NONE          0x0038
  SPI_RXOICR      NONE          0x003c
  SPI_RXUICR      NONE          0x0040
  SPI_MSTICR      NONE          0x0044
  SPI_ICR         0x0038        0x0048
  SPI_DMACR       0x003c        0x004c
  SPI_DMATDLR     0x0040        0x0050
  SPI_DMARDLR     0x0044        0x0054
  SPI_TXDR        0x0400        NONE
  SPI_RXDR        0x0800        NONE
  SPI_IDR         NONE          0x0058
  SPI_VERSION     NONE          0x005c
  SPI_DR          NONE          0x0060

- register configuration:
  such as SPI_CTRLRO in rockchip SPI controller:
    cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
        | (CR0_SSD_ONE << CR0_SSD_OFFSET);
    cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
    cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
    cr0 |= (rs->tmode << CR0_XFM_OFFSET);
    cr0 |= (rs->type << CR0_FRF_OFFSET);
  For more information, see RK3288 chip manual.

- Wait for idle: Must ensure that the FIFO data has been sent out
  before the next transfer.
Signed-off-by: Naddy ke <addy.ke@rock-chips.com>
Signed-off-by: NMark Brown <broonie@linaro.org>
      64e36824