1. 11 7月, 2012 1 次提交
  2. 30 4月, 2012 1 次提交
  3. 05 4月, 2012 3 次提交
    • J
      bna: Function name changes and cleanups · b3cc6e88
      Jing Huang 提交于
      Renamed following functions:
      bnad_cleanup_tx to bnad_destroy_tx
      bnad_free_all_txbufs to bnad_txq_cleanup
      bnad_free_txbufs to bnad_txcmpl_process
      bnad_tx to bnad_tx_complete
      bnad_cleanup_rx to bnad_destroy_rx
      bnad_reset_rcb to bnad_rcb_cleanup
      bnad_free_all_rxbufs to bnad_rxq_cleanup
      bnad_cq_cmpl_init to bnad_cq_cleanup
      bnad_alloc_n_post_rxbufs to bnad_rxq_post
      bnad_poll_cq to bnad_cq_process
      Signed-off-by: NJing Huang <huangj@brocade.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b3cc6e88
    • J
      bna: Remove tx tasklet · d95d1081
      Jing Huang 提交于
      The scheduling of tasklet and keeping the interrupts enabled makes interrupt
      reduntant. 20% of the Tx interrupts have nothing left to process or could not
      process as Tx tasklet was running.
      Signed-off-by: NJing Huang <huangj@brocade.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d95d1081
    • J
      bna: tx rx cleanup fix · 01b54b14
      Jing Huang 提交于
      This patch removes busy wait in tx/rx cleanup. bnad_cb_tx_cleanup() and
      bnad_cb_rx_cleanup() functions are called from irq context, and currently
      they do busy wait for the in-flight transmit or the currently executing napi
      polling routine to complete. To fix the issue, we create a workqueue to defer
      tx & rx cleanup processing, an in the tx rx cleanup handler, we will
      wait respective in flight processing to complete, before freeing the buffers.
      Signed-off-by: NJing Huang <huangj@brocade.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      01b54b14
  4. 01 2月, 2012 1 次提交
  5. 06 1月, 2012 1 次提交
  6. 24 12月, 2011 2 次提交
  7. 20 12月, 2011 1 次提交
  8. 09 12月, 2011 1 次提交
  9. 01 11月, 2011 1 次提交
  10. 19 10月, 2011 1 次提交
  11. 30 9月, 2011 3 次提交
  12. 22 9月, 2011 1 次提交
  13. 17 9月, 2011 2 次提交
  14. 16 9月, 2011 9 次提交
  15. 31 8月, 2011 1 次提交
  16. 27 8月, 2011 1 次提交
  17. 18 8月, 2011 1 次提交
  18. 11 8月, 2011 2 次提交
    • R
      bna: ENET and Tx Rx Redesign Enablement · 078086f3
      Rasesh Mody 提交于
      Change details:
      This patch contains additional structure and function definition changes
      that are required to enable the new msgq/enet/txrx redesign introduced
      by the previous 4 patches.
       - structure and function definition changes to header files as a result
         of Ethport, Enet, IOCEth, Tx, Rx redesign.
       - ethtool changes to use new enet function and definitions
       - Set number of Tx and Rx queues bassed on underlying hardware. Define
         separate macros for maximum and supported numbers of Tx and Rx queues
         based on underlying hardware. Take VLAN header into account for MTU
         calculation. Default to INTx mode when pci_enable_msix() fails. Set a
         bit in Rx poll routine, check and wait for that bit to be cleared in
         the cleanup routine before proceeding.
       - The TX and Rx coalesce settings are programmed in steps of 5 us. The value
         that are not divisible by 5 are rounded to the next lower number. This was
         causing the value os 1 to 4 to be rounded to 0, which is an invalid setting.
         When creating Rx and Tx object, we are currently assigning the default
         values of Rx and Tx coalescing_timeo. If these values are changed in the
         driver to a different value, the change is lost during such operations as
         MTU change. In order to avoid that, pass the configured value of
         coalescing_timeo before Rx and Tx object creation. Fix
         bnad_tx_coalescing_timeo_set() so it applies to all the Tx objects.
       - Reorg uninitialization path in case of pci_probe failure.
       - Hardware clock setup changes to pass asic generation, port modes and
         asic mode as part firmware boot parameters to firmware.
       - FW mailbox interface changes to defined asic specific mailbox interfaces.
         h/w mailbox interfaces take 8-bit FIDs and 2-bit port id for owner. Cleaned
         up mailbox definitions and usage for new and old HW. Eliminated usage of
         ASIC ID. MSI-X vector assignment and programming done by firmware. Fixed
         host offsets for CPE/RME queue registers.
       - Implement polling mechanism for FW ready to have poll mechanism replaces
         the current interrupt based FW READY method. The timer based poll routine
         in IOC will query the ioc_fwstate register to see if there is a state
         change in FW, and sends the READY event. Removed infrastructure needed to
         support mbox READY event from fw as well as IOC code.
       - Move FW init to HW init. Handle the case where PCI mapping goes away when
         IOCPF state machine is waiting for semaphore.
       - Add IOC mbox call back to client indicating that the command is sent.
      Signed-off-by: NRasesh Mody <rmody@brocade.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      078086f3
    • J
      bna: Move the Brocade driver · f844a0ea
      Jeff Kirsher 提交于
      Moves the Brocade driver into drivers/net/ethernet/brocade/ and make
      the necessary Kconfig and Makefile changes.
      
      CC: Rasesh Mody <rmody@brocade.com>
      CC: Debashis Dutt <ddutt@brocade.com>
      Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      f844a0ea
  19. 24 7月, 2011 1 次提交
  20. 23 7月, 2011 3 次提交
  21. 22 7月, 2011 1 次提交
  22. 15 7月, 2011 1 次提交
    • S
      Separate handling of irq type flags variable from the irq_flags request_irq variable · 8279171a
      Shyam Iyer 提交于
      Commit 5f77898d does not completely
      fix the problem of handling allocations with irqs disabled..  The
      below patch on top of it fixes the problem completely.
      
      Based on review by "Ivan Vecera" <ivecera@redhat.com>..
      "
      Small note, the root of the problem was that non-atomic allocation was requested with IRQs disabled. Your patch description does not contain wwhy were the IRQs disabled.
      
      The function bnad_mbox_irq_alloc incorrectly uses 'flags' var for two different things, 1) to save current CPU flags and 2) for request_irq
      call.
      First the spin_lock_irqsave disables the IRQs and saves _all_ CPU flags (including one that enables/disables interrupts) to 'flags'. Then the 'flags' is overwritten by 0 or 0x80 (IRQF_SHARED). Finally the spin_unlock_irqrestore should restore saved flags, but these flags are now either 0x00 or 0x80. The interrupt bit value in flags register on x86 arch is 0x100.
      This means that the interrupt bit is zero (IRQs disabled) after spin_unlock_irqrestore so the request_irq function is called with disabled interrupts.
      "
      Signed-off-by: NShyam Iyer <shyam_iyer@dell.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8279171a
  23. 09 7月, 2011 1 次提交