It adds PWM device driver for ZTE ZX family SoCs. The PWM controller
supports 4 devices with polarity configuration.

The driver has been tested with pwm-regulator support to scale core
voltage via cpufreq.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

This adds support for the third (optional) pwm cell to specify the
polarity, which is needed by display backlights for example.
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The rk3328 SoC supports atomic update, we could lock the configuration
of period and duty at first, after unlock is configured, the period and
duty are effective at the same time.

If the polarity, period and duty need to be configured together,
the way for atomic update is "configure lock and old polarity" ->
"configure period and duty" -> "configure unlock and new polarity".
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Just use the same PWM ops for each IP, and get rid of the ops in struct
rockchip_pwm_data, but still define the three different instances of the
struct to use common interface for each IP.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

It is usually possible to configure the polarity, cycle and duty all at
once, so that the polarity and cycle and duty are applied atomically.
Move it from rockchip_pwm_set_enable() into rockchip_pwm_config(), as
well as prepare for the next atomic update commit.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Drop the custom hook of pwm_enable() and implement pwm_apply_v1() and
pwm_apply_v2() instead.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

It seems the rockchip_pwm_config() always returns the result 0, so
remove the judge.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

New PWM module provides two individual clocks for APB clock and function
clock.
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Remove support for the SH7372 (SH-Mobile AP4) from the renesas-tpu
driver.

Commit edf41009 ("ARM: shmobile: sh7372 dtsi: Remove Legacy
file") removed this SoC from the kernel in v4.1.
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Undo preparation of a clock source if vt8500_pwm_probe() is not
successful.
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The function
static void pca9685_set_sleep_mode(struct pca9685 *pca, int sleep)
takes the chip in and out of sleep mode, depending on the value of
sleep, which is interpreted as a boolean.

To clarify that 'int sleep' is a boolean and not a sleep delay,
change the function interface to:
static void pca9685_set_sleep_mode(struct pca9685 *pca, bool enable)
Suggested-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NSven Van Asbroeck <thesven73@gmail.com>
Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: linux-pwm@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The __cros_ec_pwm_get_duty() routine was transposing the insize and
outsize fields when calling cros_ec_cmd_xfer_status().

The original code worked without error due to size of the two particular
parameter blocks passed to cros_ec_cmd_xfer_status(), so this change is
not fixing an actual runtime problem, just correcting the calling usage.
Signed-off-by: NNick Vaccaro <nvaccaro@chromium.org>
Reviewed-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

When using input clocks with high rates, such as clk81 (166MHz), the
fin_ns = NSEC_PER_SEC / fin_freq can introduce a significant error.

Ex: fin_freq = 166666667, NSEC_PER_SEC = 1000000000
    fin_ns = 5,9999999

which is, of course, rounded down to 5. This introduces an error of ~20%
on the period requested from the PWM.

This patch uses ps instead of ns (and 64 bit integers) to perform the
calculation. This should give a good enough precision.

Fixes: 211ed630 ("pwm: Add support for Meson PWM Controller")
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

squash! pwm: meson: Improve pwm calculation precision

On the gxbb (and gxl) family, the PWMs of the AO domain require a
specific compatible because the possible input clocks are different
from the EE PWMs input clocks.

Since the number of possible input clocks is also different, the
'num_parents' field is added to all the Meson PWM data.
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Remove the legacy callbacks .enable(), .disable(), .set_polarity() and
.config().
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Switch the driver to atomic PWM. This makes it easier to wait a proper
amount of time when changing the duty cycle before disabling the channel
(main use case is switching the duty cycle to 0 before disabling).
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Implement .get_state instead of only reading the polarity at probe time.
This allows to get the proper state, period and duty cycle.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

File size before:
   text	   data	    bss	    dec	    hex	filename
   1510	    296	      0	   1806	    70e	drivers/pwm/pwm-hibvt.o
File size After adding 'const':
   text	   data	    bss	    dec	    hex	filename
   1606	    192	      0	   1798	    706	drivers/pwm/pwm-hibvt.o
Signed-off-by: NArvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

In of_pwm_get(), if we fail to get the PWM chip due to probe deferal, we
shouldn't print an error message. Just be silent in this case.
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Omit an extra message for a memory allocation failure in this function.

This issue was detected by using the Coccinelle software.

Link: http://events.linuxfoundation.org/sites/events/files/slides/LCJ16-Refactor_Strings-WSang_0.pdfSigned-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.

From HW team:

	Before Tegra186, it is 48 MHz.
	In Tegra186, it is 102 MHz.

Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC chipdata.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Now that the JZ4740 and similar SoCs have a pinctrl driver, we rely on
the pins being properly configured before the driver probes.

One inherent problem of this new approach is that the pinctrl framework
does not allow us to configure each pin on demand, when the various PWM
channels are requested or released. For instance, the PWM channels can
be configured from sysfs, which would require all PWM pins to be configured
properly beforehand for the PWM function, eventually causing conflicts
with other platform or board drivers.

The proper solution here would be to modify the pwm-jz4740 driver to
handle only one PWM channel, and create an instance of this driver
for each one of the 8 PWM channels. Then, it could use the pinctrl
framework to dynamically configure the PWM pin it controls.

Until this can be done, the only jz4740 board supported upstream
(Qi lb60) can configure all of its connected PWM pins in PWM function
mode, since those are not used by other drivers nor by GPIOs on the
board.
Signed-off-by: NPaul Cercueil <paul@crapouillou.net>
Acked-by: NThierry Reding <thierry.reding@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

It is required to know the PWM clock source frequency to calculate the
PWM period.

In driver, the clock source frequency of the PWM does not get change
and, hence, get the clock source frequency in driver init. Get this
values later for period calculation from pwm_config().

This will help in avoiding the clock call for getting clock rate in the
pwm_config() each time.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

GPIO-only driver operation never clears the SLEEP bit, which can cause
the GPIOs to become unusable.

Example:
1. user requests first PWM  ->      driver clears SLEEP bit
2. user frees last PWM      ->      driver sets SLEEP bit
3. user requests GPIO
4. user switches GPIO on    ->      output does not turn on
                                    because SLEEP bit is set

Prevent this behaviour by letting the runtime PM framework control the
SLEEP bit. This will put the chip to SLEEP if no PWMs/GPIOs are exported
or in use.

Fixes: bccec89f ("Allow any of the 16 PWMs to be used as a GPIO")
Reported-by: NSven Van Asbroeck <TheSven73@googlemail.com>
Signed-off-by: NSven Van Asbroeck <TheSven73@googlemail.com>
Suggested-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

drivers/pwm/pwm-mediatek.c:210:3-8: No need to set .owner here. The core will do it.

 Remove .owner field if calls are used which set it automatically

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci

CC: John Crispin <john@phrozen.org>
Signed-off-by: NFengguang Wu <fengguang.wu@intel.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

For very short periods, the result of the division might overflow the
unsigned long hz variable (on 32-bit architectures). Avoid that by
making it an unsigned long long. While at it, also remove an unneeded
local variable whose only purpose is to store a temporary computation.
Acked-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

In some of NVIDIA Tegra's platform, PWM controller is used to
control the PWM controlled regulators. PWM signal is connected to
the VID pin of the regulator where duty cycle of PWM signal decide
the voltage level of the regulator output.

When system enters suspend, some PWM client/slave regulator devices
require the PWM output to be tristated.

Add support to configure the pin state via pinctrl frameworks in
suspend and active state of the system.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The rate of the PWM calculated as follows:

	hz = NSEC_PER_SEC / period_ns;
 	rate = (rate + (hz / 2)) / hz;

This has the precision loss in lower PWM rate.

Change this to have more precision as:

	hz = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC * 100, period_ns);
	rate = DIV_ROUND_CLOSEST(rate * 100, hz)

Example:

1. period_ns = 16672000, PWM clock rate is 200 KHz.

	Based on old formula
		hz = NSEC_PER_SEC / period_ns
		   = 1000000000ul/16672000
		   = 59 (59.98)
		rate = (200K + 59/2)/59 = 3390

	Based on new method:
		hz = 5998
		rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334

	If we measure the PWM signal rate, we will get more accurate
	period with rate value of 3334 instead of 3390.

2.  period_ns = 16803898, PWM clock rate is 200 KHz.

	Based on old formula:
		hz = 59, rate = 3390

	Based on new formula:
		hz = 5951, rate = 3360

	The PWM signal rate of 3360 is more near to requested period
	than 3333.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Use macro DIV_ROUND_CLOSEST_ULL() for 64-bit division to closest one
instead of implementing the same locally. This increase readability.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

This patch adds support for the PWM core found on current ARM base SoCs
made by MediaTek. This IP core supports 5 channels and has 2 operational
modes. There is the old mode, which is a classical PWM and the new mode
which allows the user to define bitmasks that get clocked out on the
pins. As the subsystem currently only supports PWM cores with the "old"
mode, we can safely ignore the "new" mode for now.
Signed-off-by: NJohn Crispin <john@phrozen.org>
[thierry.reding@gmail.com: minor cleanups]
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

sama5d2 can use the same atmel_pwm_data as sama5d3.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

The currently Atmel PWM controllers supported by this driver could
change period or duty factor without channel disable, for regular
channels (sama5d3 support this by using period or duty factor update
registers, sam9rl support this by writing channel update register and
select the corresponding update: period or duty factor). The chip
doesn't support run time changings of signal polarity. To take advantage
of atomic PWM framework and let controller works without glitches, in
this patch only the duty factor could be changed without disabling PWM
channel. For period and signal polarity the atomic PWM is simulated by
disabling + enabling the right PWM channel.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Implement the suspend/resume hooks to make sure the PWM device is
restored to a correct state after a suspend.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Implement the ->apply() hook and drop the ->enable(), ->disable,
->set_polarity and ->config() ones.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

If the PWM was not enabled at U-Boot loader, PWM could not work for
clock always disabled at PWM driver. The PWM clock is enabled at
beginning of pwm_apply(), but disabled at end of pwm_apply().

If the PWM was enabled at U-Boot loader, PWM clock is always enabled
unless closed by ATF. The pwm-backlight might turn off the power at
early suspend, should disable PWM clock for saving power consume.

It is important to provide opportunity to enable/disable clock at PWM
driver, the PWM consumer should ensure correct order to call PWM enable
and disable, and PWM driver ensure state of PWM clock synchronized with
PWM enabled state.

Fixes: 2bf1c98a ("pwm: rockchip: Add support for atomic update")
Cc: stable@vger.kernel.org
Signed-off-by: NDavid Wu <david.wu@rock-chips.com>
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

At least on cherrytrail, the update bit will never go low when the
enabled bit is not set.

This causes the backlight on my cube iwork8 air tablet to never turn on
again after being turned off because in the pwm_lpss_apply enable path
pwm_lpss_update will fail causing an error exit and the enable-bit to
never get set. Any following pwm_lpss_apply calls will fail the
pwm_lpss_is_updating check.

Since the docs say that the update bit should be set before the
enable-bit, split pwm_lpss_update into setting the update-bit and
pwm_lpss_wait_for_update, and move the pwm_lpss_wait_for_update call
in the enable path to after setting the enable-bit.

Fixes: 10d56a4c ("pwm: lpss: Avoid reconfiguring while UPDATE bit...")
Cc: Ilkka Koskinen <ilkka.koskinen@intel.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

As a preparation for special treatment for Broxton we split Tangier
configuration.

Fixes: b89b4b7a ("pwm: lpss: pci: Enable PWM module on Intel Edison")
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

Add a module name string to the pwm_lookup struct and if specified try
to load the module using request_module() if pwmchip_find_by_name() is
unable to find the PWM chip.

This is a last resort to work around drivers that can't - and can't be
made to - deal with deferred probe.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
[thierry.reding@gmail.com: rename new macro, reword commit message]
[thierry.reding@gmail.com: add comment explaining use-case]
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>

There is no need to hold pwm_lookup_lock after we're done with looping
over pwm_lookup_list, so release it earlier.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>