1. 09 1月, 2018 2 次提交
  2. 11 10月, 2017 3 次提交
  3. 03 8月, 2017 1 次提交
  4. 08 7月, 2017 1 次提交
  5. 06 7月, 2017 1 次提交
  6. 21 6月, 2017 1 次提交
  7. 02 5月, 2017 1 次提交
  8. 28 4月, 2017 1 次提交
    • J
      drm/i915: Eliminate HAS_HW_CONTEXTS · f2e4d76e
      Joonas Lahtinen 提交于
      HAS_HW_CONTEXTS is misleading condition for GPU reset and CCID,
      replace it with Gen specific (to be updated in next patches).
      
      HAS_HW_CONTEXTS in i915_l3_write is bogus because each HAS_L3_DPF
      match also has .has_hw_contexts = 1 set.
      
      This leads to us being able to get rid of the property completely.
      
      v2:
      - Keep the checks at Gen6 for no functional change (Ville)
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      f2e4d76e
  9. 16 3月, 2017 2 次提交
  10. 15 2月, 2017 1 次提交
  11. 27 1月, 2017 1 次提交
  12. 10 1月, 2017 1 次提交
  13. 20 12月, 2016 1 次提交
  14. 14 12月, 2016 1 次提交
  15. 02 12月, 2016 1 次提交
  16. 12 10月, 2016 1 次提交
  17. 02 9月, 2016 1 次提交
  18. 22 8月, 2016 2 次提交
  19. 28 7月, 2016 1 次提交
  20. 14 7月, 2016 2 次提交
  21. 04 7月, 2016 1 次提交
  22. 24 6月, 2016 1 次提交
  23. 24 5月, 2016 1 次提交
  24. 11 5月, 2016 1 次提交
  25. 03 3月, 2016 1 次提交
  26. 13 1月, 2016 1 次提交
  27. 10 12月, 2015 1 次提交
  28. 18 11月, 2015 1 次提交
    • V
      drm/i915: Type safe register read/write · f0f59a00
      Ville Syrjälä 提交于
      Make I915_READ and I915_WRITE more type safe by wrapping the register
      offset in a struct. This should eliminate most of the fumbles we've had
      with misplaced parens.
      
      This only takes care of normal mmio registers. We could extend the idea
      to other register types and define each with its own struct. That way
      you wouldn't be able to accidentally pass the wrong thing to a specific
      register access function.
      
      The gpio_reg setup is probably the ugliest thing left. But I figure I'd
      just leave it for now, and wait for some divine inspiration to strike
      before making it nice.
      
      As for the generated code, it's actually a bit better sometimes. Eg.
      looking at i915_irq_handler(), we can see the following change:
        lea    0x70024(%rdx,%rax,1),%r9d
        mov    $0x1,%edx
      - movslq %r9d,%r9
      - mov    %r9,%rsi
      - mov    %r9,-0x58(%rbp)
      - callq  *0xd8(%rbx)
      + mov    %r9d,%esi
      + mov    %r9d,-0x48(%rbp)
       callq  *0xd8(%rbx)
      
      So previously gcc thought the register offset might be signed and
      decided to sign extend it, just in case. The rest appears to be
      mostly just minor shuffling of instructions.
      
      v2: i915_mmio_reg_{offset,equal,valid}() helpers added
          s/_REG/_MMIO/ in the register defines
          mo more switch statements left to worry about
          ring_emit stuff got sorted in a prep patch
          cmd parser, lrc context and w/a batch buildup also in prep patch
          vgpu stuff cleaned up and moved to a prep patch
          all other unrelated changes split out
      v3: Rebased due to BXT DSI/BLC, MOCS, etc.
      v4: Rebased due to churn, s/i915_mmio_reg_t/i915_reg_t/
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Link: http://patchwork.freedesktop.org/patch/msgid/1447853606-2751-1-git-send-email-ville.syrjala@linux.intel.com
      f0f59a00
  29. 30 9月, 2015 2 次提交
  30. 15 6月, 2015 1 次提交
  31. 18 3月, 2015 1 次提交
  32. 27 2月, 2015 1 次提交
  33. 26 2月, 2015 1 次提交
    • A
      drm/i915: Removed the read of RP_STATE_CAP from sysfs/debugfs functions · bc4d91f6
      Akash Goel 提交于
      The frequency values(Rp0, Rp1, Rpn) reported by RP_STATE_CAP register
      are stored, initially by the Driver, inside the dev_priv->rps structure.
      Since these values are expected to remain same throughout, there is no real
      need to read this register, on dynamic basis, from certain debugfs/sysfs
      functions and the values can be instead retrieved from the dev_priv->rps
      structure when needed.
      For the i915_frequency_info debugfs interface, the frequency values from the
      RP_STATE_CAP register only should be used, to indicate the actual Hw state,
      since it is principally used for the debugging purpose.
      
      v2: Reverted the changes in i915_frequency_info function, to continue report
          back the frequency values, as per the actual Hw state (Chris)
      Signed-off-by: NAkash Goel <akash.goel@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      bc4d91f6