Most supported systems currently hardwire cpu_has_dsp to 0, so we also
can disable support for cpu_has_dsp2 resulting in a slightly smaller
kernel.
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

[ralf@linux-mips.org: This patch really only detects the ASE and passes its
existence on to userland via /proc/cpuinfo.  The DSP ASE Rev 2. adds new
resources but no resources that would need management by the kernel.]
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4165/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The PCI (Program Counter Interrupt) bit in the "cause" register
is mandatory for MIPS32R2 cores, but has also been added to some R1
cores (BMIPS5000). This change adds a cpu feature bit to make it
easier to check for and use this feature.
Signed-off-by: NAl Cooper <alcooperx@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4106/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

I've maintained this patch, originally from Thiemo Seufer in 2004, for a
really long time, but I think it's time for it to get a look at for
possible inclusion.  I have had no problems with it across various SGI
systems over the years.

To quote the post here:
http://www.linux-mips.org/archives/linux-mips/2004-12/msg00000.html

"the atomic functions use so far memory references for the inline
assembler to access the semaphore. This can lead to additional
instructions in the ll/sc loop, because newer compilers don't
expand the memory reference any more but leave it to the assembler.

The appended patch uses registers instead, and makes the ll/sc
arguments more explicit. In some cases it will lead also to better
register scheduling because the register isn't bound to an output
any more."
Signed-off-by: NJoshua Kinard <kumba@gentoo.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4029/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The core page allocator ensures that page flags are zeroed when freeing
pages via free_pages_check.  A number of architectures (ARM, PPC, MIPS)
rely on this property to treat new pages as dirty with respect to the data
cache and perform the appropriate flushing before mapping the pages into
userspace.

This can lead to cache synchronisation problems when using hugepages,
since the allocator keeps its own pool of pages above the usual page
allocator and does not reset the page flags when freeing a page into the
pool.

This patch adds a new architecture hook, arch_clear_hugepage_flags, so
that architectures which rely on the page flags being in a particular
state for fresh allocations can adjust the flags accordingly when a page
is freed into the pool.
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Cc: Michal Hocko <mhocko@suse.cz>
Reviewed-by: NMichal Hocko <mhocko@suse.cz>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This commit moves the driver to drivers/pwm and converts it to the new
PWM framework.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Acked-by: NLars-Peter Clausen <lars@metafoo.de>
Tested-by: NLars-Peter Clausen <lars@metafoo.de>
Acked-by: NRalf Baechle <ralf@linux-mips.org>

This is a prerequisite for allowing the PWM driver to be converted to
the PWM framework.
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Acked-by: NLars-Peter Clausen <lars@metafoo.de>
Tested-by: NLars-Peter Clausen <lars@metafoo.de>
Acked-by: NRalf Baechle <ralf@linux-mips.org>

This is a preparatory patch for the introduction of NT_SIGINFO elf note.

Make the location of compat_siginfo_t uniform across eight architectures
which have it.  Now it can be pulled in by including asm/compat.h or
linux/compat.h.

Most of the copies are verbatim.  compat_uid[32]_t had to be replaced by
__compat_uid[32]_t.  compat_uptr_t had to be moved up before
compat_siginfo_t in asm/compat.h on a several architectures (tile already
had it moved up).  compat_sigval_t had to be relocated from linux/compat.h
to asm/compat.h.
Signed-off-by: NDenys Vlasenko <vda.linux@googlemail.com>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Amerigo Wang <amwang@redhat.com>
Cc: "Jonathan M. Foote" <jmfoote@cert.org>
Cc: Roland McGrath <roland@hack.frob.com>
Cc: Pedro Alves <palves@redhat.com>
Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Set up empty UAPI Kbuild files to be populated by the header splitter.
Signed-off-by: NDavid Howells <dhowells@redhat.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: NDave Jones <davej@redhat.com>

Convert #include "..." to #include <path/...> in kernel system headers.
Signed-off-by: NDavid Howells <dhowells@redhat.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NPaul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: NDave Jones <davej@redhat.com>

Besides the CPU and DDR PLLs, the CPU and DDR frequencies
can be derived from other PLLs in the SRIF block on the
AR934x SoCs. The current code does not checks if the SRIF
PLLs are used and this can lead to incorrectly calculated
CPU/DDR frequencies.

Fix it by calculating the frequencies from SRIF PLLs if
those are used on a given board.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4324/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The MIPSsim platform is no longer supported or used.

[ralf@linux-mips.org: Also remove mipssim from arch/mips/Kbuild.platforms
and delete arch/mips/include/asm/mach-mipssim/*.]
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4350/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

If it's set, SIGPENDING is also set.  And SIGPENDING is present in
the masks...
Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Acked-by: NDavid Daney <david.daney@cavium.com>

Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
Acked-by: NDavid Daney <david.daney@cavium.com>

These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

Fix whitespace, beautify the code and remove debug statements.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

The GIC interrupt code is used by multiple platforms and the
current code was half Malta dependent code. These changes
abstract away the platform specific differences.
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

More information about the SEAD-3 platform can be found at
<http://www.mips.com/products/development-kits/mips-sead-3/>
on MTI's site. Currently, the M14K family of cores is what
the SEAD-3 is utilised with.
Signed-off-by: NDouglas Leung <douglas@mips.com>
Signed-off-by: NChris Dearman <chris@mips.com>
Signed-off-by: NSteven J. Hill <sjhill@mips.com>

Signed-off-by: NSteven J. Hill <sjhill@mips.com>

The gpio_chip struct allows us to set a .to_irq callback. Once this is set
we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing
more than one gpio_chip to register an interrupt
Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Signed-off-by: NThomas Langer <thomas.langer@lantiq.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org

Also cleanup and fix octeon_init_cvmcount()
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>

The cn68XX has a new interrupt controller named CIU2, add support for
this, and use it if cn68XX detected at runtime.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

There are 64 workqueue, 32 watchdog, and 4 mbox.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.

Add little-endian register layouts.

Patch cvmx-interrupt-rsl.c for changed definition.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

Also add cvmx_get_octeon_family().

Both of these are needed by the upcoming register definition refresh
patch.
Signed-off-by: NDavid Daney <david.daney@cavium.com>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Reviewed-by: NJonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4111/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4084/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

OHCI/EHCI are in the high (second) word.  Not currently used by any
driver.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4026/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

The USB 2.0 device depends on some functionality in other blocks, such
as GPIO and USBH.  Add those register definitions here.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4025/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4083/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

The "IUDMA" engine used by bcm63xx_enet is also used by other blocks,
such as the USB 2.0 device.  Move the definitions into a common file so
that they do not need to be duplicated in each driver.
Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4082/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4172/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

These were erroneously copied from BCM6368. BCM6328 does not expose the
ENETSW_TXDMA interrupts, and BCM_6328_HIGH_IRQ_BASE + 7 is actually used
for the second UART.
Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4090/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Add the missing definitions for BCM6345.
Signed-off-by: NMaxime Bizon <mbizon@freebox.fr>
Signed-off-by: NJonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4091/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/

Needed by SPI driver.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/3796/Signed-off-by: NJohn Crispin <blogic@openwrt.org>