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  1. 30 7月, 2014 1 次提交
    • M
      MIPS: Alchemy: clock framework integration of onchip clocks · 47440229
      由 Manuel Lauss 提交于 
      This patch introduces common clock framework integration for all
configurable on-chip clocks on Alchemy chips:

- 2 or 3 PLLs which generate integer multiples of the root rate 12MHz,
- 6 dividers which take one of the 3 PLLs as input and divide their
  rate by either multiples of 2 or 1 (Au1300).
- another bank of up to 6 muxes which take either one of the 6
  above dividers or one of the PLLs directly and divide their rate
  further by 1, 2, 3 or 4.
- a few other sources which are used by onchip peripherals and are
  informational.

This implementation will take the clock tree as it was set up
by boot firmware: all in-kernel boards should continue to work
without having to set up the clock tree in board code.

CLK_IGNORE_DISABLED will be removed once all drivers have been
converted.
Signed-off-by: NManuel Lauss <manuel.lauss@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7466/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      47440229
  3. 26 6月, 2014 1 次提交
    • R
      MIPS: Lasat: Fix build error if CRC32 is not enabled. · 16f0bbbc
      由 Ralf Baechle 提交于 
      Kconfig doesn't select CRC32 so it's possible to build a Lasat kernel
without CONFIG_CRC32 resulting in a build error:

  LD      vmlinux
arch/mips/built-in.o: In function `lasat_init_board_info':
(.text+0x22c): undefined reference to `crc32_le'
arch/mips/built-in.o: In function `lasat_write_eeprom_info':
(.text+0x7fc): undefined reference to `crc32_le'
make: *** [vmlinux] Error 1
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      16f0bbbc
  5. 02 6月, 2014 2 次提交
  7. 31 5月, 2014 3 次提交
  9. 30 5月, 2014 3 次提交
  11. 28 5月, 2014 4 次提交
    • P
      MIPS: include cpuidle Kconfig menu · c095ebaf
      由 Paul Burton 提交于 
      This patch simply includes the cpuidle Kconfig entries in preparation
for cpuidle drivers used on MIPS systems.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      c095ebaf
    • P
      MIPS: smp-cps: hotplug support · 1d8f1f5a
      由 Paul Burton 提交于 
      This patch adds support for offlining CPUs via hotplug when using the
CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2
things will happen:

  - If the CPU is part of a core which implements the MT ASE and there
    is at least one other VPE online within that core then the VPE will
    be halted by settings its TCHalt bit.

  - Otherwise if supported the core will be powered down via the CPC.

  - Otherwise the CPU will hang by executing an infinite loop.

Bringing CPUs back online is then a process of either clearing the
appropriate VPEs TCHalt bit or powering up the appropriate core via the
CPC. Throughout the process the struct core_boot_config vpe_mask field
must be maintained such that mips_cps_boot_vpes will start & stop the
correct VPEs.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      1d8f1f5a
    • P
      MIPS: pm-cps: add PM state entry code for CPS systems · 3179d37e
      由 Paul Burton 提交于 
      This patch adds code to generate entry & exit code for various low power
states available on systems based around the MIPS Coherent Processing
System architecture (ie. those with a Coherence Manager, Global
Interrupt Controller & for >=CM2 a Cluster Power Controller). States
supported are:

  - Non-coherent wait. This state first leaves the coherent domain and
    then executes a regular MIPS wait instruction. Power savings are
    found from the elimination of coherency interventions between the
    core and any other coherent requestors in the system.

  - Clock gated. This state leaves the coherent domain and then gates
    the clock input to the core. This removes all dynamic power from the
    core but leaves the core at the mercy of another to restart its
    clock. Register state is preserved, but the core can not service
    interrupts whilst its clock is gated.

  - Power gated. This deepest state removes all power input to the core.
    All register state is lost and the core will restart execution from
    its BEV when another core powers it back up. Because register state
    is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
    implementation in order for the core to exit the state successfully.

The code will detect which states are available on the current system
during boot & generate the entry/exit code for those states. This will
be used by cpuidle & hotplug implementations.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      3179d37e
    • T
      MIPS: SNI: Remove USE_GENERIC_EARLY_PRINTK_8250 · 5ec79bf9
      由 Thomas Bogendoerfer 提交于 
      SNI RM code has its own EARLY_PRINTK support no need for some generic 8250
stuff.
Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6715/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5ec79bf9
  13. 24 5月, 2014 2 次提交
  15. 23 5月, 2014 1 次提交
  17. 02 5月, 2014 1 次提交
  19. 24 4月, 2014 1 次提交
  21. 08 4月, 2014 1 次提交
  23. 01 4月, 2014 4 次提交
  25. 31 3月, 2014 1 次提交
  27. 27 3月, 2014 13 次提交
  29. 18 3月, 2014 1 次提交
  31. 17 3月, 2014 1 次提交
    • P
      MIPS: mark O32+FP64 experimental for now · 06e2e882
      由 Paul Burton 提交于 
      Commit 597ce172 "MIPS: Support for 64-bit FP with O32 binaries"
introduced support for setting Status.FR=1 for O32 binaries with the
EF_MIPS_FP64 ELF header flag set. Whilst this flag is currently
supported by binutils it does introduce an ABI break within userland.
Objects built with EF_MIPS_FP64 cannot be safely linked with those built
without it since code in either object may assume behaviour specific to
a value of FR.

More recently there has been discussion around avoiding further
fragmentation of the O32 ABI whilst still allowing the use of FR=1 and
features such as MSA which depend upon it. Details of the plan to allow
this are still being worked on, and whilst the kernel will need the
ability to handle FR=1 with O32 tasks it is unclear what else it may
need to provide to a userland which seeks to avoid another ABI break. In
order to prevent the proliferation of userland which may rely upon the
current EF_MIPS_FP64 behaviour this patch marks the kernel support for
it experimental & disables it by default. Under current proposals it is
likely that this support can simply be enabled again later, but possibly
after the introduction of further interfaces with userland and support
for the MIPS R5 UFR feature.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: Matthew Fortune <matthew.fortune@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Paul Burton <paul.burton@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/6549/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      06e2e882