1. 21 5月, 2013 1 次提交
    • T
      pci: PCIe driver for Marvell Armada 370/XP systems · 45361a4f
      Thomas Petazzoni 提交于
      This driver implements the support for the PCIe interfaces on the
      Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
      cover earlier families of Marvell SoCs, such as Dove, Orion and
      Kirkwood.
      
      The driver implements the hw_pci operations needed by the core ARM PCI
      code to setup PCI devices and get their corresponding IRQs, and the
      pci_ops operations that are used by the PCI core to read/write the
      configuration space of PCI devices.
      
      Since the PCIe interfaces of Marvell SoCs are completely separate and
      not linked together in a bus, this driver sets up an emulated PCI host
      bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
      interface.
      
      In addition, this driver enumerates the different PCIe slots, and for
      those having a device plugged in, it sets up the necessary address
      decoding windows, using the mvebu-mbus driver.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Acked-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NJason Cooper <jason@lakedaemon.net>
      45361a4f
  2. 08 5月, 2013 2 次提交
  3. 30 4月, 2013 9 次提交
  4. 29 4月, 2013 1 次提交
  5. 28 4月, 2013 1 次提交
  6. 26 4月, 2013 2 次提交
  7. 25 4月, 2013 2 次提交
  8. 24 4月, 2013 3 次提交
  9. 20 4月, 2013 1 次提交
    • A
      ata: arasan: remove the need for platform_data · e34d3865
      Arnd Bergmann 提交于
      This adds a complete DT binding for the arasan device driver. There is
      currently only one user, which is the spear13xx platform, so we don't
      actually have to parse all the properties until another user comes in,
      but this does use the generic DMA binding to find the DMA channel.
      
      The patch is untested so far and is part of a series to convert
      the spear platform over to use the generic DMA binding, so it
      should stay with the rest of the series.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Acked-by: NViresh Kumar <viresh.linux@linaro.org>
      Cc: Vinod Koul <vinod.koul@intel.com>
      Cc: Jeff Garzik <jgarzik@redhat.com>
      Cc: devicetree-discuss@lists.ozlabs.org
      e34d3865
  10. 19 4月, 2013 1 次提交
  11. 18 4月, 2013 1 次提交
  12. 17 4月, 2013 2 次提交
  13. 16 4月, 2013 4 次提交
  14. 15 4月, 2013 1 次提交
    • D
      ARM: socfpga: Add clock entries into device tree · 042000b0
      Dinh Nguyen 提交于
      Adds the main PLL clock groups for SOCFPGA into device tree file
      so that the clock framework to query the clock and clock rates
      appropriately.
      
      $cat /sys/kernel/debug/clk/clk_summary
         clock                        enable_cnt  prepare_cnt  rate
      ---------------------------------------------------------------------
       osc1                           2           2            25000000
          sdram_pll                   0           0            400000000
             s2f_usr2_clk             0           0            66666666
             ddr_dq_clk               0           0            200000000
             ddr_2x_dqs_clk           0           0            400000000
             ddr_dqs_clk              0           0            200000000
          periph_pll                  2           2            500000000
             s2f_usr1_clk             0           0            50000000
             per_base_clk             4           4            100000000
             per_nand_mmc_clk         0           0            25000000
             per_qsi_clk              0           0            250000000
             emac1_clk                1           1            125000000
             emac0_clk                0           0            125000000
          main_pll                    1           1            1600000000
             cfg_s2f_usr0_clk         0           0            100000000
             main_nand_sdmmc_clk      0           0            100000000
             main_qspi_clk            0           0            400000000
             dbg_base_clk             0           0            400000000
             mainclk                  0           0            400000000
             mpuclk                   1           1            800000000
                smp_twd               1           1            200000000
      Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
      Reviewed-by: NPavel Machek <pavel@denx.de>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      042000b0
  15. 13 4月, 2013 4 次提交
  16. 12 4月, 2013 5 次提交