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  1. 03 7月, 2014 3 次提交
    • W
      iommu/arm-smmu: remove support for chained SMMUs · 44680eed
      由 Will Deacon 提交于 
      The ARM SMMU driver has supported chained SMMUs (i.e. SMMUs connected
back-to-back in series) via the smmu-parent property in device tree.
This was in anticipation of somebody building such a configuration,
however that seems not to be the case.

This patch removes the unused chained SMMU hack from the driver. We can
consider adding it back later if somebody decided they need it, but for
the time being it's just pointless mess that we're carrying in mainline.

Removal of the feature also makes migration to the generic IOMMU bindings
easier.
Signed-off-by: NWill Deacon <will.deacon@arm.com>
      44680eed
    • W
      iommu/arm-smmu: caps: add IOMMU_CAP_INTR_REMAP capability · d0948945
      由 Will Deacon 提交于 
      MSIs are just seen as bog standard memory writes by the ARM SMMU, so
they can be translated (and isolated) in the same way.

This patch adds the IOMMU_CAP_INTR_REMAP capability to the ARM SMMU
driver and reworks our capabaility code so that we don't assume the
caps are organised as bits in a bitmask (since this isn't the intention).
Signed-off-by: NWill Deacon <will.deacon@arm.com>
      d0948945
    • W
      iommu/arm-smmu: add support for PCI master devices · a9a1b0b5
      由 Will Deacon 提交于 
      This patch extends the ARM SMMU driver so that it can handle PCI master
devices in addition to platform devices described in the device tree.

The driver is informed about the PCI host controller in the DT via a
phandle to the host controller in the mmu-masters property. The host
controller is then added to the master tree for that SMMU, just like a
normal master (although it probably doesn't advertise any StreamIDs).

When a device is added to the PCI bus, we set the archdata.iommu pointer
for that device to describe its StreamID (actually its RequesterID for
the moment). This allows us to re-use our existing data structures using
the host controller of_node for everything apart from StreamID
configuration, where we reach into the archdata for the information we
require.

Cc: Varun Sethi <varun.sethi@freescale.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
      a9a1b0b5
  3. 02 7月, 2014 1 次提交
  5. 05 6月, 2014 1 次提交
    • A
      intel-iommu: integrate DMA CMA · 36746436
      由 Akinobu Mita 提交于 
      This adds support for the DMA Contiguous Memory Allocator for
intel-iommu.  This change enables dma_alloc_coherent() to allocate big
contiguous memory.

It is achieved in the same way as nommu_dma_ops currently does, i.e.
trying to allocate memory by dma_alloc_from_contiguous() and
alloc_pages() is used as a fallback.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Don Dutile <ddutile@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Andi Kleen <andi@firstfloor.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      36746436
  7. 31 5月, 2014 2 次提交
  9. 28 5月, 2014 1 次提交
  11. 27 5月, 2014 1 次提交
  13. 26 5月, 2014 21 次提交
  15. 16 5月, 2014 3 次提交
  17. 14 5月, 2014 7 次提交
    • B
      iommu/exynos: Remove unnecessary "&" from function pointers · ba5fa6f6
      由 Bjorn Helgaas 提交于 
      Remove unnecessary "&" from function pointers in exynos_iommu_ops.
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      ba5fa6f6
    • C
      iommu/exynos: Apply workaround of caching fault page table entries · 66a7ed84
      由 Cho KyongHo 提交于 
      This patch contains 2 workaround for the System MMU v3.x.

System MMU v3.2 and v3.3 has FLPD cache that caches first level page
table entries to reduce page table walking latency. However, the
FLPD cache is filled with a first level page table entry even though
it is not accessed by a master H/W because System MMU v3.3
speculatively prefetches page table entries that may be accessed
in the near future by the master H/W.
The prefetched FLPD cache entries are not invalidated by iommu_unmap()
because iommu_unmap() only unmaps and invalidates the page table
entries that is mapped.

Because exynos-iommu driver discards a second level page table when
it needs to be replaced with another second level page table or
a first level page table entry with 1MB mapping, It is required to
invalidate FLPD cache that may contain the first level page table
entry that points to the second level page table.

Another workaround of System MMU v3.3 is initializing the first level
page table entries with the second level page table which is filled
with all zeros. This prevents System MMU prefetches 'fault' first
level page table entry which may lead page fault on access to 16MiB
wide.

System MMU 3.x fetches consecutive page table entries by a page
table walking to maximize bus utilization and to minimize TLB miss
panelty.
Unfortunately, functional problem is raised with the fetching behavior
because it fetches 'fault' page table entries that specifies no
translation information and that a valid translation information will
be written to in the near future. The logic in the System MMU generates
page fault with the cached fault entries that is no longer coherent
with the page table which is updated.

There is another workaround that must be implemented by I/O virtual
memory manager: any two consecutive I/O virtual memory area must have
a hole between the two that is larger than or equal to 128KiB.
Also, next I/O virtual memory area must be started from the next
128KiB boundary.

0            128K           256K               384K             512K
|-------------|---------------|-----------------|----------------|
|area1---------------->|.........hole...........|<--- area2 -----

The constraint is depicted above.
The size is selected by the calculation followed:
 - System MMU can fetch consecutive 64 page table entries at once
   64 * 4KiB = 256KiB. This is the size between 128K ~ 384K of the
   above picture. This style of fetching is 'block fetch'. It fetches
   the page table entries predefined consecutive page table entries
   including the entry that is the reason of the page table walking.
 - System MMU can prefetch upto consecutive 32 page table entries.
   This is the size between 256K ~ 384K.
Signed-off-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      66a7ed84
    • C
      iommu/exynos: Turn on useful configuration options · eeb5184b
      由 Cho KyongHo 提交于 
      This turns on FLPD_CACHE, ACGEN and SYSSEL.

FLPD_CACHE is a cache of 1st level page table entries that contains
the address of a 2nd level page table to reduce latency of page table
walking.

ACGEN is architectural clock gating that gates clocks by System MMU
itself if it is not active. Note that ACGEN is different from clock
gating by the CPU. ACGEN just gates clocks to the internal logic of
System MMU while clock gating by the CPU gates clocks to the System
MMU.

SYSSEL selects System MMU version in some Exynos SoCs. Some Exynos
SoCs have an option to select System MMU versions exclusively because
the SoCs adopts new System MMU version experimentally.

This also always selects LRU as TLB replacement policy. Selecting TLB
replacement policy is deprecated from System MMU 3.2. TLB in System
MMU 3.3 has single TLB replacement policy, LRU. The bit of MMU_CFG
selecting TLB replacement policy is remained as reserved.

QoS value of page table walking is set to 15 (highst value). System
MMU 3.3 can inherit QoS value of page table walking from its master
H/W's transaction. This new feature is enabled by default and QoS
value written to MMU_CFG is ignored.

This patch also adds simplifies the sysmmu version checking by
introducing some macros.
Signed-off-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      eeb5184b
    • C
      iommu/exynos: Support for device tree · 6b21a5db
      由 Cho KyongHo 提交于 
      This commit adds device tree support for System MMU.

Also, system mmu handling is improved. Previously, an IOMMU domain is
bound to a System MMU which is not correct. This patch binds an IOMMU
domain with the master device of a System MMU.
Signed-off-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      6b21a5db
    • C
      iommu/exynos: Enhanced error messages · 0bf4e54d
      由 Cho KyongHo 提交于 
      Some redundant error message is removed and some error messages
are changed to error level from debug level.
Signed-off-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      0bf4e54d
    • A
      iommu/exynos: Add devices attached to the System MMU to an IOMMU group · bf4a1c92
      由 Antonios Motakis 提交于 
      Patch written by Antonios Motakis <a.motakis@virtualopensystems.com>:

IOMMU groups are expected by certain users of the IOMMU API,
e.g. VFIO. Since each device is behind its own System MMU, we
can allocate a new IOMMU group for each device.
Reviewed-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NAntonios Motakis <a.motakis@virtualopensystems.com>
Signed-off-by: NShaik Ameeer Basha <shaik.ameer@samsung.com>
Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      bf4a1c92
    • C
      iommu/exynos: Use exynos-iommu specific typedef · d09d78fc
      由 Cho KyongHo 提交于 
      This commit introduces sysmmu_pte_t for page table entries and
sysmmu_iova_t vor I/O virtual address that is manipulated by
exynos-iommu driver. The purpose of the typedef is to remove
dependencies to the driver code from the change of CPU architecture
from 32 bit to 64 bit.
Signed-off-by: NCho KyongHo <pullip.cho@samsung.com>
Signed-off-by: NShaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: NJoerg Roedel <jroedel@suse.de>
      d09d78fc