1. 30 8月, 2005 6 次提交
    • D
      [SPARC64]: Make debugging spinlocks usable again. · 442464a5
      David S. Miller 提交于
      When the spinlock routines were moved out of line into
      kernel/spinlock.c this made it so that the debugging
      spinlocks record lock acquisition program counts in the
      kernel/spinlock.c functions not in their callers.
      This makes the debugging info kind of useless.
      
      So record the correct caller's program counter and
      now this feature is useful once more.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      442464a5
    • K
      [SPARC64]: remove use of asm/segment.h · 3d6364ab
      Kumar Gala 提交于
      Removed sparc64 architecture specific users of asm/segment.h and
      asm-sparc64/segment.h itself
      Signed-off-by: NKumar Gala <kumar.gala@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3d6364ab
    • D
      [SPARC64]: Revamp Spitfire error trap handling. · 6c52a96e
      David S. Miller 提交于
      Current uncorrectable error handling was poor enough
      that the processor could just loop taking the same
      trap over and over again.  Fix things up so that we
      at least get a log message and perhaps even some register
      state.
      
      In the process, much consolidation became possible,
      particularly with the correctable error handler.
      
      Prefix assembler and C function names with "spitfire"
      to indicate that these are for Ultra-I/II/IIi/IIe only.
      
      More work is needed to make these routines robust and
      featureful to the level of the Ultra-III error handlers.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6c52a96e
    • D
      [SPARC64]: Do not call winfix_dax blindly · bde4e4ee
      David S. Miller 提交于
      Verify we really are taking a data access exception trap, at TL1, from
      one of the window spill/fill handlers.
      
      Else call a new function, data_access_exception_tl1, to log the error.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bde4e4ee
    • D
      [SPARC64]: Fix trap state reading for instruction_access_exception. · 5ea68e02
      David S. Miller 提交于
      1) Read ASI_IMMU SFSR not ASI_DMMU.
      2) IMMU has no SFAR, read TPC instead
      3) Delete old and incorrect comment about the DTLB protection
         trap having a dependency on the SFSR contents in order to
         function correctly
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5ea68e02
    • S
      [PATCH] convert signal handling of NODEFER to act like other Unix boxes. · 69be8f18
      Steven Rostedt 提交于
      It has been reported that the way Linux handles NODEFER for signals is
      not consistent with the way other Unix boxes handle it.  I've written a
      program to test the behavior of how this flag affects signals and had
      several reports from people who ran this on various Unix boxes,
      confirming that Linux seems to be unique on the way this is handled.
      
      The way NODEFER affects signals on other Unix boxes is as follows:
      
      1) If NODEFER is set, other signals in sa_mask are still blocked.
      
      2) If NODEFER is set and the signal is in sa_mask, then the signal is
      still blocked. (Note: this is the behavior of all tested but Linux _and_
      NetBSD 2.0 *).
      
      The way NODEFER affects signals on Linux:
      
      1) If NODEFER is set, other signals are _not_ blocked regardless of
      sa_mask (Even NetBSD doesn't do this).
      
      2) If NODEFER is set and the signal is in sa_mask, then the signal being
      handled is not blocked.
      
      The patch converts signal handling in all current Linux architectures to
      the way most Unix boxes work.
      
      Unix boxes that were tested:  DU4, AIX 5.2, Irix 6.5, NetBSD 2.0, SFU
      3.5 on WinXP, AIX 5.3, Mac OSX, and of course Linux 2.6.13-rcX.
      
      * NetBSD was the only other Unix to behave like Linux on point #2. The
      main concern was brought up by point #1 which even NetBSD isn't like
      Linux.  So with this patch, we leave NetBSD as the lonely one that
      behaves differently here with #2.
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      69be8f18
  2. 25 8月, 2005 1 次提交
  3. 20 8月, 2005 1 次提交
  4. 19 8月, 2005 1 次提交
  5. 10 8月, 2005 1 次提交
    • A
      [NET]: Fix memory leak in sys_{send,recv}msg() w/compat · d64d3873
      Andrew Morton 提交于
      From: Dave Johnson <djohnson+linux-kernel@sw.starentnetworks.com>
      
      sendmsg()/recvmsg() syscalls from o32/n32 apps to a 64bit kernel will
      cause a kernel memory leak if iov_len > UIO_FASTIOV for each syscall!
      
      This is because both sys_sendmsg() and verify_compat_iovec() kmalloc a
      new iovec structure.  Only the one from sys_sendmsg() is free'ed.
      
      I wrote a simple test program to confirm this after identifying the
      problem:
      
      http://davej.org/programs/testsendmsg.c
      
      Note that the below fix will break solaris_sendmsg()/solaris_recvmsg() as
      it also calls verify_compat_iovec() but expects it to malloc internally.
      
      [ I fixed that. -DaveM ]
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d64d3873
  6. 09 8月, 2005 1 次提交
  7. 05 8月, 2005 1 次提交
    • J
      [PATCH] PCI: restore BAR values after D3hot->D0 for devices that need it · fec59a71
      John W. Linville 提交于
      Some PCI devices (e.g. 3c905B, 3c556B) lose all configuration
      (including BARs) when transitioning from D3hot->D0.  This leaves such
      a device in an inaccessible state.  The patch below causes the BARs
      to be restored when enabling such a device, so that its driver will
      be able to access it.
      
      The patch also adds pci_restore_bars as a new global symbol, and adds a
      correpsonding EXPORT_SYMBOL_GPL for that.
      
      Some firmware (e.g. Thinkpad T21) leaves devices in D3hot after a
      (re)boot.  Most drivers call pci_enable_device very early, so devices
      left in D3hot that lose configuration during the D3hot->D0 transition
      will be inaccessible to their drivers.
      
      Drivers could be modified to account for this, but it would
      be difficult to know which drivers need modification.  This is
      especially true since often many devices are covered by the same
      driver.  It likely would be necessary to replicate code across dozens
      of drivers.
      
      The patch below should trigger only when transitioning from D3hot->D0
      (or at boot), and only for devices that have the "no soft reset" bit
      cleared in the PM control register.  I believe it is safe to include
      this patch as part of the PCI infrastructure.
      
      The cleanest implementation of pci_restore_bars was to call
      pci_update_resource.  Unfortunately, that does not currently exist
      for the sparc64 architecture.  The patch below includes a null
      implemenation of pci_update_resource for sparc64.
      
      Some have expressed interest in making general use of the the
      pci_restore_bars function, so that has been exported to GPL licensed
      modules.
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      fec59a71
  8. 28 7月, 2005 2 次提交
  9. 27 7月, 2005 1 次提交
  10. 25 7月, 2005 2 次提交
  11. 13 7月, 2005 1 次提交
  12. 12 7月, 2005 2 次提交
  13. 11 7月, 2005 6 次提交
  14. 09 7月, 2005 2 次提交
  15. 07 7月, 2005 1 次提交
  16. 06 7月, 2005 2 次提交
  17. 05 7月, 2005 5 次提交
    • D
      [SPARC64]: Fix IRQ retry interval timer value on sparc64 PCI controllers. · 864ae180
      David S. Miller 提交于
      Use '5' instead of 'infinity'.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      864ae180
    • D
      [SPARC64]: Small Schizo PCI controller programming tweaks. · 9fba62a5
      David S. Miller 提交于
      Use macro instead of magic value for Tomatillo discard-
      timeout interrupt enable register bit.
      
      Leave OBP programming PTO value unless Tomatillo and
      version >= 0x2.
      
      If no-bus-parking property is present, explicitly clear
      PCICTRL_PARK bit.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9fba62a5
    • D
      [SPARC64]: Do proper DMA IRQ syncing on Tomatillo · bb6743f4
      David S. Miller 提交于
      This was the main impetus behind adding the PCI IRQ shim.
      
      In order to properly order DMA writes wrt. interrupts, you have to
      write to a PCI controller register, then poll for that bit clearing.
      There is one bit for each interrupt source, and setting this register
      bit tells Tomatillo to drain all pending DMA from that device.
      
      Furthermore, Tomatillo's with revision less than 4 require us to do a
      block store due to some memory transaction ordering issues it has on
      JBUS.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bb6743f4
    • D
      [SPARC64]: Add support for IRQ pre-handlers. · 088dd1f8
      David S. Miller 提交于
      This allows a PCI controller to shim into IRQ delivery
      so that DMA queues can be drained, if necessary.
      
      If some bus specific code needs to run before an IRQ
      handler is invoked, the bus driver simply needs to setup
      the function pointer in bucket->irq_info->pre_handler and
      the two args bucket->irq_info->pre_handler_arg[12].
      
      The Schizo PCI driver is converted over to use a pre-handler
      for the DMA write-sync processing it needs when a device
      is behind a PCI->PCI bus deeper than the top-level APB
      bridges.
      
      While we're here, clean up all of the action allocation
      and handling.  Now, we allocate the irqaction as part of
      the bucket->irq_info area.  There is an array of 4 irqaction
      (for PCI irq sharing) and a bitmask saying which entries
      are active.
      
      The bucket->irq_info is allocated at build_irq() time, not
      at request_irq() time.  This simplifies request_irq() and
      free_irq() tremendously.
      
      The SMP dynamic IRQ retargetting code got removed in this
      change too.  It was disabled for a few months now, and we
      can resurrect it in the future if we want.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      088dd1f8
    • R
      [SPARC64/COMPAT]: Add some compat ioctl for ppdev · e7270dec
      Raphael Assenat 提交于
      The following patch adds some ioctls to include/linux/compat_ioctl.h
      to allow using ppdev from the 32 bit user space on sparc64.
      
      This patch also adds the PPDEV option in the sparc64 menu, near Parallel
      printer support in the 'General machine setup' submenu.
      
      All those ioctls seem to be compatible, since (correct me if I'm wrong)
      they dont use the 'long' type. See include/linux/ppdev.h.
      
      The application I used to test the new ioctls only used the following:
      PPEXCL
      PPCLAIM
      PPNEGOT
      PPGETMODES
      PPRCONTROL
      PPWCONTROL
      PPDATADIR
      PPWDATA
      PPRDATA
      
      But I beleive that the other ioctls will work fine.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      e7270dec
  18. 28 6月, 2005 2 次提交
    • D
      [SPARC64]: Get rid of fast IRQ feature. · 63b61452
      David S. Miller 提交于
      The only real user was the assembler floppy interrupt
      handler, which does not need to be in assembly.
      
      This makes it so that there are less pieces of code which
      know about the internal layout of ivector_table[] and
      friends.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      63b61452
    • D
      [SPARC64]: Avoid membar instructions in delay slots. · b445e26c
      David S. Miller 提交于
      In particular, avoid membar instructions in the delay
      slot of a jmpl instruction.
      
      UltraSPARC-I, II, IIi, and IIe have a bug, documented in
      the UltraSPARC-IIi User's Manual, Appendix K, Erratum 51
      
      The long and short of it is that if the IMU unit misses
      on a branch or jmpl, and there is a store buffer synchronizing
      membar in the delay slot, the chip can stop fetching instructions.
      
      If interrupts are enabled or some other trap is enabled, the
      chip will unwedge itself, but performance will suffer.
      
      We already had a workaround for this bug in a few spots, but
      it's better to have the entire tree sanitized for this rule.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b445e26c
  19. 24 6月, 2005 2 次提交