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  1. 29 3月, 2011 4 次提交
  3. 24 3月, 2011 5 次提交
  5. 23 3月, 2011 1 次提交
  7. 21 3月, 2011 2 次提交
    • M
      powerpc/ptrace: Remove BUG_ON when full register set not available · a71f5d5d
      由 Mike Wolf 提交于 
      In some cases during a threaded core dump not all the threads will have
a full register set. This happens when the signal causing the core dump
races with a thread exiting.  The race happens when the exiting thread
has entered the kernel for the last time before the signal arrives, but
doesn't get far enough through the exit code to avoid being included
in the core dump.

So we get a thread included in the core dump which is never going to go
out to userspace again and only has a partial register set recorded

Normally we would catch each thread as it is about to go into userspace
and capture the full register set then.

However, this exiting thread is never going to go out to userspace
again, so we have no way to capture its full register set.  It doesn't
really matter, though, as this is a thread which is effectively
already dead.

So instead of hitting a BUG() in this case (a really bad choice of
action in the first place), we use a poison value for the register
values.

[BenH]: Some cosmetic/stylistic changes and fix build on ppc32
Signed-off-by: NMike Wolf <mjw@linux.vnet.ibm.com>
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      a71f5d5d
    • B
      powerpc/pci: Fix crash in PCI code on ppc64 when matching device nodes · 90407c99
      由 Benjamin Herrenschmidt 提交于 
      Commit b5d937de has a bug which causes
basically a NULL dereference in the PCI code during boot on ppc64
machines.

fetch_dev_dn() is called when dev->dev.of_node is NULL, so using that
as the starting point for the search makes no sense. It should instead
start from the device node of the PHB.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      90407c99
  9. 16 3月, 2011 1 次提交
  11. 10 3月, 2011 2 次提交
  13. 04 3月, 2011 1 次提交
  15. 02 3月, 2011 6 次提交
  17. 28 2月, 2011 2 次提交
  19. 07 2月, 2011 2 次提交
  21. 05 2月, 2011 2 次提交
  23. 02 2月, 2011 1 次提交
  25. 25 1月, 2011 1 次提交
    • T
      percpu: align percpu readmostly subsection to cacheline · 19df0c2f
      由 Tejun Heo 提交于 
      Currently percpu readmostly subsection may share cachelines with other
percpu subsections which may result in unnecessary cacheline bounce
and performance degradation.

This patch adds @cacheline parameter to PERCPU() and PERCPU_VADDR()
linker macros, makes each arch linker scripts specify its cacheline
size and use it to align percpu subsections.

This is based on Shaohua's x86 only patch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Cc: Shaohua Li <shaohua.li@intel.com>
      19df0c2f
  27. 21 1月, 2011 10 次提交