1. 09 3月, 2011 16 次提交
  2. 08 2月, 2011 2 次提交
  3. 28 1月, 2011 2 次提交
    • M
      microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1 · 9c749e17
      Michal Simek 提交于
      Unaligned code use shift for finding register operand.
      There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1
      by
      	ori rD, r0, (1 << imm);	\
      	idivu rD, rD, rA
      
      but if rD is equal rA then ori instruction rewrite value which
      should be devide.
      
      The patch remove this macro which use idivu instruction because
      idivu takes 32/34 cycles. The highest shifting is 20 which takes
      20 cycles.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      9c749e17
    • M
      microblaze: Fix DTB passing from bootloader · 026a2078
      Michal Simek 提交于
      Little endian system needs to check OF_DT_HEADER
      but it is swapped because it is in big-endian.
      Microblaze LE provides lwr instruction which loads
      magic number in BIG endian format which can be compared.
      
      There is used the fact that if you write 0x1 as word
      and load it as byte then you get for big-endian zero
      and 1 for little-endian.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      026a2078
  4. 16 1月, 2011 1 次提交
  5. 03 1月, 2011 4 次提交
  6. 18 11月, 2010 2 次提交
  7. 01 11月, 2010 1 次提交
  8. 28 10月, 2010 2 次提交
  9. 22 10月, 2010 1 次提交
  10. 21 10月, 2010 9 次提交