This is here most likely since the FSL bsp. Back in the FSL bsp it was
set to 50Mhz and working. However the driver divided the SoC freq. only
by 2. According to the TRM the platform clock (which the manual refers
in its formula) is the system clock divided by two. So in the end it has
to divide by 4 and this is what the fsl-spi driver in tree is doing.
Since then the flash is not wokring I guess. After chaning the freq from
50Mhz to 40Mhz like others do then I can access the flash.
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

It is not at 0xffa00000. According to current u-boot source the NAND
controller is always at 0xff800000 and it is either at CS0 or CS1
depending on NAND or NAND+NOR mode. In 36bit mode it is shifted to
0xfff800000 but it has always an eight there and never an A.
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add usb2 controller node for P1020RDB, P2020RDB, P2020DS, P1021MDS
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Systems which use the fsl_pq_mdio driver need to specify an
address for TBI PHY transactions such that the address does
not conflict with any PHYs on the bus (all transactions to
that address are directed to the onboard TBI PHY). The driver
used to scan for a free address if no address was specified,
however this ran into issues when the PHY Lib was fixed so
that all MDIO transactions were protected by a mutex. As it
is, the code was meant to serve as a transitional tool until
the device trees were all updated to specify the TBI address.

The best fix for the mutex issue was to remove the scanning code,
but it turns out some of the newer SoCs have started to omit
the tbi-phy node when SGMII is not being used. As such, these
devices will now fail unless we add a tbi-phy node to the first
mdio controller.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Utilize new split between board & SoC, and new SoC device trees split
into pre & post utilizing 'template' includes for SoC IP blocks.

Other changes include:

* Moved to specifying interrupt-parent for mpic at root
* Moved to 4-cell mpic interrupt cells to support MPIC timers
* Reworked PCIe nodes to allow supportin IRQs for controller (errors) and
  moved PCI device IRQs down to virtual bridge level
* Updated spi node to new espi binding specification
* Renamed 'sdhci' node to 'sdhc'
* Changed GPIO compatiable from 'fsl,mpc8572-gpio' to 'fsl,pq3-gpio' as the
 'mpc8572' compatiable is to deal with a 'mpc8572' specific to an erratum
* Fixed wrong reg offsets for mdio nodes associated with etsec2 &
* etsec3
* Dropping "fsl,p2020-IP..." from compatibles for standard blocks
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps, one alarm, and the PPS callback.
Signed-off-by: NRichard Cochran <richard.cochran@omicron.at>
Acked-by: NDavid S. Miller <davem@davemloft.net>
Acked-by: NJohn Stultz <john.stultz@linaro.org>
Signed-off-by: NJohn Stultz <john.stultz@linaro.org>

PCIe device in legacy mode can trigger interrupts using the wires #INTA,
#INTB ,#INTC and #INTD. PCI devices are obligated to use #INTx for
interrupts under legacy mode.  Each PCI slot or device is typically wired
to different inputs on the interrupt controller.

So, Define interrupt-map and interrupt-map-mask properties for device tree
to of map each PCI interrupt signal to the inputs of the interrupt
controller.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Creates P2020si.dtsi, containing information for P2020 SoC. Modifies dts
files for P2020 based systems to use dtsi file.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

PCIe memory address space is 1:1 mapped with u-boot.

Update dts of Px020RDB i.e. P1020RDB and P2020RDB to match the address map
changes in u-boot.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for the P2020RDB reference board from Freescale.

Overview of P2020RDB platform
	- DDR
	  DDR2 1G
	- NOR Flash
	  16MByte
	- NAND Flash
	  32MByte
	- 3 Ethernet interfaces
	  1) etSEC1
		- RGMII
		- connected to a 5 port Vitesse Switch(VSC7385)
		- Switch is memory mapped through eLBC interface(CS#2)
		- IRQ1
	  2) etSEC2
		- SGMII
		- connected to VSC8221
		- IRQ2
	  3) etSEC3
		- RGMII
		- connected to VSC8641
		- IRQ3
	- 2 1X PCIe interfaces
	- SD/MMC ,USB
	- SPI EEPROM
	- Serial I2C EEPROM
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P2020 is a dual e500v2 core based SOC with:
* 3 PCIe controllers
* 2 General purpose DMA controllers
* 2 sRIO controllers
* 3 eTSECS
* USB 2.0
* SDHC
* SPI, I2C, DUART
* enhanced localbus
* and optional Security (P2020E) security w/XOR acceleration

The p2020 DS reference board is pretty similar to the existing MPC85xx
DS boards and has a ULI 1575 connected on one of the PCIe controllers.
Signed-off-by: NTed Peters <Ted.Peters@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level.  It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The cell-index property isn't used on PCI nodes and is ill defined.
Remove it for now and if someone comes up with a good reason and
consistent definition for it we can add it back
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Currently it doesn't matter where the mdio nodes are placed, but with
power management support (i.e. when sleep = <> properties will take
effect), mdio nodes placement will become important: mdio controller
is a part of the ethernet block, so the mdio nodes should be placed
correctly. Otherwise we may wrongly assume that MDIO controllers are
available during sleep.
Suggested-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The PCI IO region sizes where incorrectly set to 1M instead of 64k.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The localbus node flash had a minor typo for a read-only property.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The PCIe interrupts for 8544ds and 8572ds were incorrect.  The 8572 case
was found by Liu Yu.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Does the same for the accompanying MDIO driver, and then modifies the TBI
configuration method.  The old way used fields in einfo, which no longer
exists.  The new way is to create an MDIO device-tree node for each instance
of gianfar, and create a tbi-handle property to associate ethernet controllers
with the TBI PHYs they are connected to.
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Fix the localbus reg & range properties to respect that the top
level #address-cells and #size-cells = 2.  The original commit
(c64ef80b) did not do that.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Also add NOR and NAND flash partitions for mpc8572ds board
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

It's 1MB, not 512KB.  Newer U-Boots will fix this entry, but that's no
reason to have the wrong value in the dts.
Signed-off-by: NTrent Piepho <tpiepho@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Change the top-level #address-cells and #size-cells to <2> so the
mpc8572ds.dts is easier to deal with both a true 32-bit physical
or 36-bit physical address space.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

add simple-bus compatible property to soc nodes for 83xx/85xx platforms
that were missing them.  Add same to platform probe code.

This fixes SoC device drivers (such as talitos) to succeed in matching
devices present in the soc node.

also update mpc836x_rdk dts to new SEC bindings (overlooked in commit
3fd44736: powerpc/fsl: update crypto node definition and device tree
instances).
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

delete obsolete device-type property, delete model property
(use compatible property instead), prepend "fsl," to Freescale
specific properties. Add nodes to device trees that are missing them,
and fix broken property values in other trees.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Added DMA nodes for the elo/elo-plus DMA engines.

Renamed the interrupt controller alias in mpc832x_rdb.dts to ipic so that
its the same as all the other boards.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Added next-level-cache to the L1 and a reference to the new L2 label.
This is per the ePAPR 0.94 spec.  Since we are't really dependent on this
today we aren't supporting the "legacy" l2-cache phandle that is specified
in the PPC v2.1 OF Binding spec.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Removed clock-frequency, big-endian, and built-in props as they aren't
specified anywhere.  Also added compatible = "chrp,open-pic" in the
places it was missing.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This patch enabled MSI on 8544ds and 8572ds board.
So far only one MSI interrupt can generate on 8544 board.
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The 8572 is a dual core processor, not reason not to describe both
cores in the device tree.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The ULI based boards had the interrupt maps for USB on the ULI incorrectly
set.

Also, the MPC8572DS was missing the interrupt-map-mask for the 3rd PCIe
controller.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Added aliases nodes for kurobox, 83xx, 85xx, and 86xx platforms.
This included added labels and cell-index properties for serial and
pci nodes.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Removed address fields in ethernet nodes
* Removed #address-cells, #size-cells from gianfar nodes
* Added cell-index to gianfar and ucc ethernet nodes
* Added enet[0..3] labels
* Renamed compatible node for gianfar mdio to "fsl,gianfar-mdio"
* Removed device_type = "mdio"

The matching for gianfar mdio still supports the old "mdio"/"gianfar" combo
but it is now considered deprecated.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Removed device_type = "i2c"
* Added missing second I2C controller on MPC8548 CDS, MPC8544 DS
* Added #address-cells, #size-cells, and cell-index where missing
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The interrupt map for the PCI PHB that had the ULI1575 was not correct
on the boards that have it.

* 8544 DS:
   - Fix interrupt mask
   - Be explicit about use of INTA for on chip peripherals

* 8572 DS/8641 HPCN:
   - Fix interrupt mask
   - Expand interrupt map for PCI slots to cover all functions
   - Be explicit about use of INTA for on chip peripherals
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Added basic board port for MPC8572 DS reference platform that is
similiar to the MPC8544/33 DS reference platform in uniprocessor mode.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>