The patch replaces all CTR_OVERFLOWED macros. 64 bit MSR functions and
64 bit counter values are used now. Thus, it will be easier to later
extend the models to use more than 32 bit width counters.
Signed-off-by: NRobert Richter <robert.richter@amd.com>

This patch introduces op_x86_get_ctrl() to calculate the value of the
performance control register. This is generic code usable for all
models. The event and reserved masks are model specific and stored in
struct op_x86_model_spec. 64 bit MSR functions are used now. The patch
removes many hard to read macros used for ctrl calculation.

The function op_x86_get_ctrl() is common code and the first step to
further merge performance counter implementations for x86 models.
Signed-off-by: NRobert Richter <robert.richter@amd.com>

In follow-on patches the setup_ctrs() functions will need data that
describes the model. This patch extends the function argument list to
pass a pointer of the model to these function.
Signed-off-by: NRobert Richter <robert.richter@amd.com>

This patch fixes missing braces around macro parameters. Macro
definitions from intel_arch_perfmon.h are used where possible.
Signed-off-by: NRobert Richter <robert.richter@amd.com>

The macros CTRL_READ() and CTRL_WRITE() make the code hard to read and
maintain. This patch replaces them by rdmsr()/wrmsr() functions and
simplifies the code.
Signed-off-by: NRobert Richter <robert.richter@amd.com>

There are duplicate macro implementations in model specific code. This
patch moves all common macros to op_x86_model.h.
Signed-off-by: NRobert Richter <robert.richter@amd.com>

The function arch_perfmon_init() in nmi_int.c is model specific. This
patch moves it to op_model_ppro.c by using the init function pointer
in struct op_x86_model_spec.

Cc: Andi Kleen <ak@linux.intel.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>

This reverts commit 59512900.

arch_perfmon_setup_counters() is actually never called for ppro, so
there is no code that changes the numbers in op_ppro_spec. The patch
as it is has no effect.

Cc: Andi Kleen <ak@linux.intel.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>

Impact: fix stuck NMIs and non-working oprofile on certain CPUs

Resetting the counter width of the performance counters on Intel's
Core2 CPUs, breaks the delivery of NMIs, when running in x86_64 mode.

This should fix bug #12395:

  http://bugzilla.kernel.org/show_bug.cgi?id=12395Signed-off-by: NTim Blechmann <tim@klingt.org>
Signed-off-by: NRobert Richter <robert.richter@amd.com>
LKML-Reference: <20090303100412.GC10085@erda.amd.com>
Cc: <stable@kernel.org>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

Impact: cleanup

Remove genapic.h and remove all references to it.
Signed-off-by: NIngo Molnar <mingo@elte.hu>

- make oprofile build
- select X86_X2APIC from X86_UV - it relies on it
- export genapic for oprofile modular build
Signed-off-by: NIngo Molnar <mingo@elte.hu>

If oprofile statically compiled in kernel, a cpu unplug triggers
a panic in ppro_stop(), because a NULL pointer is dereferenced.
Signed-off-by: NEric Dumazet <dada1@cosmosbay.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>

reset_value was changed from long to u64 in commit
b9917028 (oprofile: Implement Intel
architectural perfmon support)

But dynamic allocation of this array use a wrong type (long instead of
u64)

Cc: Andi Kleen <ak@linux.intel.com>
Signed-off-by: NEric Dumazet <dada1@cosmosbay.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>

Fix the counter overflow check for CPUs with counter width > 32

I had a similar change in a different patch that I didn't submit
and I didn't notice the problem earlier because it was always
tested together.
Signed-off-by: NAndi Kleen <ak@linux.intel.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>

Signed-off-by: NRobert Richter <robert.richter@amd.com>

Discover number of counters for all family 6 models even when not
in arch perfmon mode.
Signed-off-by: NAndi Kleen <ak@linux.intel.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>

Newer Intel CPUs (Core1+) have support for architectural
events described in CPUID 0xA. See the IA32 SDM Vol3b.18 for details.

The advantage of this is that it can be done without knowing about
the specific CPU, because the CPU describes by itself what
performance events are supported. This is only a fallback
because only a limited set of 6 events are supported.
This allows to do profiling on Nehalem and on Atom systems
(later not tested)

This patch implements support for that in oprofile's Intel
Family 6 profiling module. It also has the advantage of supporting
an arbitary number of events now as reported by the CPU.
Also allow arbitary counter widths >32bit while we're at it.

Requires a patched oprofile userland to support the new
architecture.

v2: update for latest oprofile tree
    remove force_arch_perfmon
Signed-off-by: NAndi Kleen <ak@linux.intel.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>

Reverting commit 1a960b40 for the main
branch. Multiplexing will be tracked on a separate feature branch.

Conflicts:

    arch/x86/oprofile/nmi_int.c

This patch introduces multiplexing support for the Oprofile kernel
module. It basically adds a new function pointer in oprofile_operator
allowing each architecture to supply its callback to switch between
different sets of event when the timer expires. Userspace tools can
modify the time slice through /dev/oprofile/time_slice.

It also modifies the number of counters exposed to the userspace through
/dev/oprofile. For example, the number of counters for AMD CPUs are
changed to 32 and multiplexed in the sets of 4.
Signed-off-by: NJason Yeh <jason.yeh@amd.com>
Signed-off-by: NRobert Richter <robert.richter@amd.com>
Cc: oprofile-list <oprofile-list@lists.sourceforge.net>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

no code changed:

arch/x86/oprofile/op_model_ppro.o:
   text    data     bss     dec     hex filename
   1765       0      16    1781     6f5 op_model_ppro.o.before
   1765       0      16    1781     6f5 op_model_ppro.o.after
md5:
71c7f68d2197d686e3d1121bc18a6b6e  op_model_ppro.o.before.asm
71c7f68d2197d686e3d1121bc18a6b6e  op_model_ppro.o.after.asm
Signed-off-by: NPaolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NIngo Molnar <mingo@elte.hu>

Handle these 32 bit perfmon counter MSR writes cleanly in oprofile.
Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

Need to enable/disable all the counters instead of just counter 0.

This affects all cpus with family=6, including i386/core.  Usual symptom:
only counter 0 provides samples.  Other counters don't produce samples.
Signed-off-by: NArun Sharma <arun.sharma@google.com>
Cc: Philippe Elie <phil.el@wanadoo.fr>
Cc: John Levon <levon@movementarian.org>
Signed-off-by: NAndrew Morton <akpm@osdl.org>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Incorporates the new performance counter reservation system in oprofile.
Also cleans up a lot of the initialization code.  The code original zero'd
out every register associated with performance counters regardless if those
registers were used or not.  This causes issues with the nmi watchdog.
Now oprofile tries to reserve registers and gives up if it can't get them.

Cc: levon@movementarian.org
Cc: oprofile-list@lists.sf.net
Signed-off-by: NDon Zickus <dzickus@redhat.com>
Signed-off-by: NAndi Kleen <ak@suse.de>

Misc header cleanup for nmi watchdog.
Signed-off-by: NDon Zickus <dzickus@redhat.com>
Signed-off-by: NAndi Kleen <ak@suse.de>
Signed-off-by: NLinus Torvalds <torvalds@osdl.org>

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!