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  1. 31 12月, 2008 3 次提交
  3. 21 12月, 2008 6 次提交
  5. 16 12月, 2008 1 次提交
  7. 04 12月, 2008 2 次提交
  9. 03 12月, 2008 1 次提交
  11. 01 12月, 2008 1 次提交
    • A
      powerpc/mpic: Don't reset affinity for secondary MPIC on boot · cc353c30
      由 Arnd Bergmann 提交于 
      Kexec/kdump currently fails on the IBM QS2x blades when the kexec happens
on a CPU other than the initial boot CPU.  It turns out that this is the
result of mpic_init trying to set affinity of each interrupt vector to the
current boot CPU.

As far as I can tell,  the same problem is likely to exist on any
secondary MPIC, because they have to deliver interrupts to the first
output all the time. There are two potential solutions for this: either
not set up affinity at all for secondary MPICs, or assume that a single
CPU output is connected to the upstream interrupt controller and hardcode
affinity to that per architecture.

This patch implements the second approach, defaulting to the first output.
Currently, all known secondary MPICs are routed to their upstream port
using the first destination, so we hardcode that.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cc353c30
  13. 19 11月, 2008 1 次提交
  15. 15 11月, 2008 1 次提交
  17. 14 11月, 2008 1 次提交
  19. 31 10月, 2008 2 次提交
    • K
      powerpc/mpic: Fix regression caused by change of default IRQ affinity · 3c10c9c4
      由 Kumar Gala 提交于 
      The Freescale implementation of MPIC only allows a single CPU destination
for non-IPI interrupts.  We add a flag to the mpic_init to distinquish
these variants of MPIC.  We pull in the irq_choose_cpu from sparc64 to
select a single CPU as the destination of the interrupt.

This is to deal with the fact that the default smp affinity was
changed by commit 18404756 ("genirq:
Expose default irq affinity mask (take 3)") to be all CPUs.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      3c10c9c4
    • T
      gianfar: Fix race in TBI/SerDes configuration · c132419e
      由 Trent Piepho 提交于 
      The init_phy() function attaches to the PHY, then configures the
SerDes<->TBI link (in SGMII mode).  The TBI is on the MDIO bus with the PHY
(sort of) and is accessed via the gianfar's MDIO registers, using the
functions gfar_local_mdio_read/write(), which don't do any locking.

The previously attached PHY will start a work-queue on a timer, and
probably an irq handler as well, which will talk to the PHY and thus use
the MDIO bus.  This uses phy_read/write(), which have locking, but not
against the gfar_local_mdio versions.

The result is that PHY code will try to use the MDIO bus at the same time
as the SerDes setup code, corrupting the transfers.

Setting up the SerDes before attaching to the PHY will insure that there is
no race between the SerDes code and *our* PHY, but doesn't fix everything.
Typically the PHYs for all gianfar devices are on the same MDIO bus, which
is associated with the first gianfar device.  This means that the first
gianfar's SerDes code could corrupt the MDIO transfers for a different
gianfar's PHY.

The lock used by phy_read/write() is contained in the mii_bus structure,
which is pointed to by the PHY.  This is difficult to access from the
gianfar drivers, as there is no link between a gianfar device and the
mii_bus which shares the same MDIO registers.  As far as the device layer
and drivers are concerned they are two unrelated devices (which happen to
share registers).

Generally all gianfar devices' PHYs will be on the bus associated with the
first gianfar.  But this might not be the case, so simply locking the
gianfar's PHY's mii bus might not lock the mii bus that the SerDes setup
code is going to use.

We solve this by having the code that creates the gianfar platform device
look in the device tree for an mdio device that shares the gianfar's
registers.  If one is found the ID of its platform device is saved in the
gianfar's platform data.

A new function in the gianfar mii code, gfar_get_miibus(), can use the bus
ID to search through the platform devices for a gianfar_mdio device with
the right ID.  The platform device's driver data is the mii_bus structure,
which the SerDes setup code can use to lock the current bus.
Signed-off-by: NTrent Piepho <tpiepho@freescale.com>
CC: Andy Fleming <afleming@freescale.com>
Signed-off-by: NJeff Garzik <jgarzik@redhat.com>
      c132419e
  21. 18 10月, 2008 1 次提交
  23. 14 10月, 2008 5 次提交
  25. 13 10月, 2008 1 次提交
  27. 02 10月, 2008 1 次提交
  29. 29 9月, 2008 1 次提交
  31. 24 9月, 2008 1 次提交
  33. 23 9月, 2008 1 次提交
  35. 17 9月, 2008 1 次提交
  37. 14 9月, 2008 1 次提交
  39. 05 9月, 2008 1 次提交
    • L
      mv643xx_eth: remove force_phy_addr field · ac840605
      由 Lennert Buytenhek 提交于 
      Currently, there are two different fields in the
mv643xx_eth_platform_data struct that together describe the PHY
address -- one field (phy_addr) has the address of the PHY, but if
that address is zero, a second field (force_phy_addr) needs to be
set to distinguish the actual address zero from a zero due to not
having filled in the PHY address explicitly (which should mean
'use the default PHY address').

If we are a bit smarter about the encoding of the phy_addr field,
we can avoid the need for a second field -- this patch does that.
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      ac840605
  41. 02 9月, 2008 1 次提交
  43. 28 8月, 2008 1 次提交
  45. 24 8月, 2008 1 次提交
  47. 21 8月, 2008 2 次提交
  49. 20 8月, 2008 2 次提交