1. 14 9月, 2008 1 次提交
  2. 10 9月, 2008 3 次提交
  3. 06 9月, 2008 5 次提交
  4. 05 9月, 2008 1 次提交
  5. 04 9月, 2008 2 次提交
  6. 03 9月, 2008 3 次提交
    • L
      Split up PIT part of TSC calibration from native_calibrate_tsc · ec0c15af
      Linus Torvalds 提交于
      The TSC calibration function is still very complicated, but this makes
      it at least a little bit less so by moving the PIT part out into a
      helper function of its own.
      Tested-by: NLarry Finger <Larry.Finger@lwfinger.net>
      Signed-of-by: NLinus Torvalds <torvalds@linux-foundation.org>
      ec0c15af
    • T
      [x86] Fix TSC calibration issues · fbb16e24
      Thomas Gleixner 提交于
      Larry Finger reported at http://lkml.org/lkml/2008/9/1/90:
      An ancient laptop of mine started throwing errors from b43legacy when
      I started using 2.6.27 on it. This has been bisected to commit bfc0f594
      "x86: merge tsc calibration".
      
      The unification of the TSC code adopted mostly the 64bit code, which
      prefers PMTIMER/HPET over the PIT calibration.
      
      Larrys system has an AMD K6 CPU. Such systems are known to have
      PMTIMER incarnations which run at double speed. This results in a
      miscalibration of the TSC by factor 0.5. So the resulting calibrated
      CPU/TSC speed is half of the real CPU speed, which means that the TSC
      based delay loop will run half the time it should run. That might
      explain why the b43legacy driver went berserk.
      
      On the other hand we know about systems, where the PIT based
      calibration results in random crap due to heavy SMI/SMM
      disturbance. On those systems the PMTIMER/HPET based calibration logic
      with SMI detection shows better results.
      
      According to Alok also virtualized systems suffer from the PIT
      calibration method.
      
      The solution is to use a more wreckage aware aproach than the current
      either/or decision.
      
      1) reimplement the retry loop which was dropped from the 32bit code
      during the merge. It repeats the calibration and selects the lowest
      frequency value as this is probably the closest estimate to the real
      frequency
      
      2) Monitor the delta of the TSC values in the delay loop which waits
      for the PIT counter to reach zero. If the maximum value is
      significantly different from the minimum, then we have a pretty safe
      indicator that the loop was disturbed by an SMI.
      
      3) keep the pmtimer/hpet reference as a backup solution for systems
      where the SMI disturbance is a permanent point of failure for PIT
      based calibration
      
      4) do the loop iteration for both methods, record the lowest value and
      decide after all iterations finished.
      
      5) Set a clear preference to PIT based calibration when the result
      makes sense.
      
      The implementation does the reference calibration based on
      HPET/PMTIMER around the delay, which is necessary for the PIT anyway,
      but keeps separate TSC values to ensure the "independency" of the
      resulting calibration values.
      
      Tested on various 32bit/64bit machines including Geode 266Mhz, AMD K6
      (affected machine with a double speed pmtimer which I grabbed out of
      the dump), Pentium class machines and AMD/Intel 64 bit boxen.
      Bisected-by: NLarry Finger <Larry.Finger@lwfinger.net>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Tested-by: NLarry Finger <Larry.Finger@lwfinger.net>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      fbb16e24
    • L
      Un-break printk strings in x86 PCI probing code · 011fec74
      Linus Torvalds 提交于
      Breaking lines due to some imaginary problem with a long line length is
      often stupid and wrong, but never more so when it splits a string that
      is printed out into multiple lines.  This really ended up making it much
      harder to find where some error strings were printed out, because a
      simple 'grep' didn't work.
      
      I'm sure there is tons more of this particular idiocy hiding in other
      places, but this particular case hit me once more last week. So fix it.
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      011fec74
  7. 30 8月, 2008 1 次提交
  8. 28 8月, 2008 2 次提交
  9. 27 8月, 2008 2 次提交
  10. 26 8月, 2008 6 次提交
  11. 25 8月, 2008 5 次提交
  12. 24 8月, 2008 1 次提交
  13. 23 8月, 2008 3 次提交
    • R
      x86 MCE: Fix CPU hotplug problem with multiple multicore AMD CPUs · 8735728e
      Rafael J. Wysocki 提交于
      During CPU hot-remove the sysfs directory created by
      threshold_create_bank(), defined in
      arch/x86/kernel/cpu/mcheck/mce_amd_64.c, has to be removed before
      its parent directory, created by mce_create_device(), defined in
      arch/x86/kernel/cpu/mcheck/mce_64.c .  Moreover, when the CPU in
      question is hotplugged again, obviously the latter has to be created
      before the former.  At present, the right ordering is not enforced,
      because all of these operations are carried out by CPU hotplug
      notifiers which are not appropriately ordered with respect to each
      other.  This leads to serious problems on systems with two or more
      multicore AMD CPUs, among other things during suspend and hibernation.
      
      Fix the problem by placing threshold bank CPU hotplug callbacks in
      mce_cpu_callback(), so that they are invoked at the right places,
      if defined.  Additionally, use kobject_del() to remove the sysfs
      directory associated with the kobject created by
      kobject_create_and_add() in threshold_create_bank(), to prevent the
      kernel from crashing during CPU hotplug operations on systems with
      two or more multicore AMD CPUs.
      
      This patch fixes bug #11337.
      Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
      Acked-by: NAndi Kleen <andi@firstfloor.org>
      Tested-by: NMark Langsdorf <mark.langsdorf@amd.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      8735728e
    • R
      x86: fix: make PCI ECS for AMD CPUs hotplug capable · 91ede005
      Robert Richter 提交于
      Until now, PCI ECS setup was performed at boot time only and for cpus
      that are enabled then. This patch fixes this and adds cpu hotplug.
      
      Tests sequence (check if ECS bit is set when bringing cpu online again):
      
       # ( perl -e 'sysseek(STDIN, 0xC001001F, 0)'; hexdump -n 8 -e '2/4 "%08x " "\n"' )   < /dev/cpu/1/msr
       00000008 00404010
       # ( perl -e 'sysseek(STDOUT, 0xC001001F, 0); print pack "l*", 8, 0x00400010' ) > /dev/cpu/1/msr
       # ( perl -e 'sysseek(STDIN, 0xC001001F, 0)'; hexdump -n 8 -e '2/4 "%08x " "\n"' )   < /dev/cpu/1/msr
       00000008 00400010
       # echo 0 > /sys/devices/system/cpu/cpu1/online
       # echo 1 > /sys/devices/system/cpu/cpu1/online
       # ( perl -e 'sysseek(STDIN, 0xC001001F, 0)'; hexdump -n 8 -e '2/4 "%08x " "\n"' )   < /dev/cpu/1/msr
       00000008 00404010
      Reported-by: NYinghai Lu <yhlu.kernel@gmail.com>
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      91ede005
    • R
      x86: fix: do not run code in amd_bus.c on non-AMD CPUs · 9b4e27b5
      Robert Richter 提交于
      Jan Beulich wrote:
      
      > Even worse - this would even try to access the MSR on non-AMD CPUs
      > (currently probably prevented just by the fact that only AMD ones use
      > family values of 0x10 or higher).
      
      This patch adds cpu vendor check to the postcore_initcalls.
      Reported-by: NJan Beulich <jbeulich@novell.com>
      Signed-off-by: NRobert Richter <robert.richter@amd.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      9b4e27b5
  14. 22 8月, 2008 5 次提交