Add support for the RTC unit on JZ4740 SoCs.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Paul Gortmaker <p_gortmaker@yahoo.com>
Cc: rtc-linux@googlegroups.com
Acked-by: NWan ZongShun <mcuos.com@gmail.com>
Cc: linux-mips@linux-mips.org 
Cc: linux-kernel@vger.kernel.org
Cc: Alessandro Zummo <a.zummo@towertech.it>,
Patchwork: https://patchwork.linux-mips.org/patch/1424/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add the Kbuild files for the JZ4740 architecture and adds JZ4740 support
to the MIPS Kbuild files.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1406/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add platform devices for all the JZ4740 platform drivers.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1469/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for initializing arcs_cmdline on JZ4740 based machines and
provides a prom_putchar implementation.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1404/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The JZ4740 UART interface is almost 16550 compatible.
The UART module needs to be enabled by setting a bit in the FCR register
and it has support for receive timeout interrupts.  Instead of adding yet
another machine specific quirk to the 8250 serial driver we provide a
serial_out implementation which sets the required additional flags.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1403/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for the PWM part of the timer unit on a JZ4740 SoC.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1468/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for DMA transfers on JZ4740 SoCs.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1401/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add gpiolib support for JZ4740 SoCs.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1467/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add plat_mem_setup and get_system_type for JZ4740 SoCs.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1399/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for suspend/resume and poweroff/reboot on a JZ4740 SoC.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1398/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add clocksource and clockevent support for the timer/counter unit on
JZ4740 SoCs.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1397/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for the timer/counter unit on a JZ4740 SoC.  This code is used
as a common base for the JZ4740 clocksource/clockevent implementation and
PWM support.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1396/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for IRQ handling on a JZ4740 SoC.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1465/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for managing the clocks found on JZ4740 SoC through the
Linux clock API.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1466/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code.
It also adds the iomem addresses for the different components found on
a JZ4740 SoC.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1464/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

* Rename camel-case InitTLBStart_addr to octeon_bootloader_entry_addr.

* Convert calls to cvmx_read64_uint32(), to simple pointer
  dereferences.

* Set proper ebase.

* Don't confuse coreid and cpu numbers.

* Try to maintain consistent bootloader coremask.

* Update the signature and boot_init_vector of supported bootloaders.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1491/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1490/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Also number offline CPUs that could potentially be brought on-line
later.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1489/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The use of handle_percpu_irq() is not really what we want for MSI, use
handle_simple_irq() instead.  This is probably the prototypical case
for using handle_simple_irq(), because all the MSIs are dispatched from
the root interrupt service routine.

Also since the base IRQ is not shared, don't pass IRQF_SHARED.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1488/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

MSI IRQ numbers are allocated dynamically, so there is no reason to
have all these static definitions.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1487/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The original version went behind the back of everything, leaving
things in an inconsistent state.

Now we use the irq_set_affinity() to do the work for us.  This has the
advantage that the IRQ core's view of the affinity stays consistent.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1486/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The main change is to change most of the IRQs from handle_percpu_irq
to handle_fasteoi_irq.  This necessitates extracting all the .ack code
to common functions that are not exposed to the irq core.

The affinity code now acts more sanely, by doing round-robin
distribution instead of broadcasting.

Because of the change to handle_fasteoi_irq and affinity, some of the
IRQs had to be split into separate groups with their own struct
irq_chip to prevent undefined operations on specific IRQ lines.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1485/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Put all the MSI code in one place (msi-octeon.c).  This simplifies
octeon-irq.c and gets rid of some ugly #ifdefs
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1484/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

From: Wolfgang Grandegger <wg@denx.de>

Add basic support for the General Purpose Router (GPR) board from
Trapeze ITS.
Signed-off-by: NWolfgang Grandegger <wg@denx.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1460/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

au1000_eth uses firmware calls to get a valid MAC address, and changes
it depending on platform device id.  This patch moves this logic out of
the driver into the platform device registration part, where boards with
supported chips can use whatever firmware interface they need; the default
implementation maintains compatibility with existing, YAMON-based firmware.
Tested-by: NWolfgang Grandegger <wg@denx.de>
Acked-by: NFlorian Fainelli <florian@openwrt.org>
Signed-off-by: NManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: netdev@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1481/Acked-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Remove the SERIAL_8250_AU1X00 config symbol.  Instead, use the MIPS_ALCHEMY
one which is always defined when building an Au1x00-based platform.
Signed-off-by: NManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Linux-serial <linux-serial@vger.kernel.org>
Patchwork: https://patchwork.linux-mips.org/patch/1461/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This one depends on a previous patch (which removes SOC_AU1X00 and changes
MACH_ALCHEMY) to apply cleanly (and then actually work), so I'd love for
this to go in via the mips tree.

Remove the CONFIG_SOC_AU1X00 Kconfig symbol since its job can also be done
by MACH_ALCHEMY, now renamed to MIPS_ALCHEMY.
Signed-off-by: NManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/1461/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add support for the external T-cache interface. Allow for platform
independent size probing from 512KB to 8MB in powers of two.
Signed-off-by: NRicardo Mendoza <ricmm@gentoo.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1477/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Small cleanup of the cache code to get rid of inline asm, in preparation
to give tertiary cache support.
Signed-off-by: NRicardo Mendoza <ricmm@gentoo.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1476/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The commit "MIPS: Tracing: Cleanup the arguments passing of
prepare_ftrace_return" has moved the "jal     prepare_ftrace_return"
instruction after the handling of the 3rd argument but forgot to remove
the superfluous space before the related instructions.
Signed-off-by: NWu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1475/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Based somewhat on the PPC implementation.

32-bit processes have the heap randomized in an 8MB space, 256MB for
64-bit processes.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1479/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Fairly straight forward: For 32-bit address spaces randomize within a
16MB space, for 64-bit within a 256MB space.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1480/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add some comments about mtx1_pci_idsel() and remove a dead block of old code.
Signed-off-by: NBruno Randolf <br1@einfach.org>
To: linux-mips@linux-mips.org
To: manuel.lauss@googlemail.com
Cc: florian@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/1449/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

* Remove unnecessary 'if (int_status & (1 <<10))' statement
* s/if (foo != 0)/if (foo)/
* Remove unused 'inst_status &= ~(1 << i);' line
Signed-off-by: NShinya Kuribayashi <skuribay@pobox.com>
To: wuzhangjin@gmail.com
CC: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1433/Acked-by: NWu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Don't duplicate worthless lines.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1390/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Don't duplicate worthless lines.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1389/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Although all EMMAxxx SoCs can support IP2 and IP3 hardware interrupts,
current EMMA2RH plat_irq_dispatch() supports IP2 only.  We can make it
configurable in the future, but for the time being, would like to make
things explicitly allcated to IP2 in accordance with plat_irq_dispatch().
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1388/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

For historical reasons, we used to put MIPS CPU IRQs behind SoC-specific
IRQs in the queue, and have been using CPU_IRQ_BASE as MIPS_CPU_IRQ_BASE.
In recent years, however, we've brought it back to normal order, and now
CPU_IRQ_BASE just redefines the generic MIPS_CPU_IRQ_BASE.

At the same time, NUM_CPU_IRQ is also removed as useless.
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1387/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

OCTEON implements __builtin_popcount with a single instruction, so lets use it.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/1431/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Some MIPS ISA processor varients can do hweight operations
efficiently.

Split arch_hweight.h into a seperate file, and implement the
operations with __builtin_popcount{,ll} if supported.
Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: David Daney <ddaney@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/1430/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>