- 03 2月, 2011 15 次提交
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由 Russell King 提交于
Limit DMA_CACHE_RWFO to only v6k SMP CPUs - V6 CPUs aren't SMP capable, so the read/write for ownership work-around doesn't apply to them. Acked-by: NWill Deacon <will.deacon@arm.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
SMP extensions are only supported on ARMv6k or ARMv7 architectures, so only offer the option if we're building for such an architecture. Acked-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Now that we build a v6+v6k+v7 kernel with -march=armv6k for everything, we don't need to disable swp emulation to work around the build problem with OMAP. Tested-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
CPU_32v6K controls whether we use the ARMv6K extension instructions in the kernel, and in some places whether we use SMP-safe code sequences (eg, bitops.) MX3 prevents the selection of this option to ensure that it is not enabled for their CPU, which is ARMv6 only. Now that we've split the CPU_V6 option, V6K support won't be offered for MX3 anymore. OMAP prevents the selection of this option in an attempt to produce a kernel which runs on architectures from ARMv6 to ARMv7 MPCore. We now achieve this in a different way (see the previous patches). As such, we no longer need to offer this as a configuration option to the user. Tested-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Rather than turning off CPU domain switching when the build architecture includes ARMv6K, thereby causing problems for ARMv6-supporting kernels, turn it on when it's required to support a CPU architecture. Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
If CONFIG_CPU_V6 is enabled, we may or may not have the TLS register. Use the conditional code which copes with this variability. Otherwise, if CONFIG_CPU_32v6K is set, we know we have the TLS register on all supported CPUs, so use it unconditionally. Acked-by: NNicolas Pitre <nicolas.pitre@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
If CONFIG_CPU_V6 is enabled, avoid using the double-word exclusive instructions in the kernel's atomic implementations as these are not supported. Fall back to the generic spinlock code instead. Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NWill Deacon <will.deacon@arm.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
If CONFIG_CPU_V6 is enabled, we must avoid the byte/halfword/doubleword exclusive operations, which aren't implemented before V6K. Use the generic versions (or omit them) instead. If CONFIG_CPU_V6 is not set, but CONFIG_CPU_32v6K is enabled, we have the K extnesions, so use these new instructions. Acked-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
If CONFIG_CPU_V6 is enabled, then the kernel must support ARMv6 CPUs which don't have the V6K extensions implemented. Always use the dummy store-exclusive method to ensure that the exclusive monitors are cleared. If CONFIG_CPU_V6 is not set, but CONFIG_CPU_32v6K is enabled, then we have the K extensions available on all CPUs we're building support for, so we can use the new clear-exclusive instruction. Acked-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Make Dove platforms select the new V6K CPU option. Tested-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Make Realview EB ARM11MPCore and PB11MPCore select the new V6K CPU option. Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Introduce a CPU_V6K configuration option for platforms to select if they have a V6K CPU core. This allows us to identify whether we need to support ARMv6 CPUs without the V6K SMP extensions at build time. Currently CPU_V6K is just an alias for CPU_V6, and all places which reference CPU_V6 are replaced by (CPU_V6 || CPU_V6K). Select CPU_V6K from platforms which are known to be V6K-only. Acked-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
SMP requires at least the ARMv6K extensions to be present, so if we're running on SMP, the WFE and SEV instructions must be available. However, when we run on UP, the v6K extensions may not be available, and so we don't want WFE/SEV to be in the instruction stream. Use the SMP alternatives infrastructure to replace these instructions with NOPs if we build for SMP but run on UP. Tested-by: NTony Lindgren <tony@atomide.com> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Switch the set/clear/change bitops to use the word-based exclusive operations, which are only present in a wider range of ARM architectures than the byte-based exclusive operations. Tested record: - Nicolas Pitre: ext3,rw,le - Sourav Poddar: nfs,le - Will Deacon: ext3,rw,le - Tony Lindgren: ext3+nfs,le Reviewed-by: NNicolas Pitre <nicolas.pitre@linaro.org> Tested-by: NSourav Poddar <sourav.poddar@ti.com> Tested-by: NWill Deacon <will.deacon@arm.com> Tested-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Add additional instructions to our assembly bitops functions to ensure that they only operate on word-aligned pointers. This will be necessary when we switch these operations to use the word-based exclusive operations. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 25 1月, 2011 3 次提交
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由 Russell King 提交于
Update the option text to those which appear on the front of the appropriate board user guides. This gives consistent board naming, and makes it obvious which option is for which platform. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
As no one seems to really know which configuration options tie up with which boards, I thought I'd do some investigation and try to work it out. After discussion with some folk in linaro, I think I have this nailed. The names are updated to use the name on the front of the appropriate board user guide for the various baseboards, which I've taken to be the official name for each board. I haven't significantly updated the descriptions for the tiles as that is even less clear - as far as I can see on ARMs website, there is no Cortex-A9 tile for Realview EB - only ARM11MPCore, ARM1156T2F-S, ARM1176TZF-S and Cortex-R4F. So exactly what this 'Multicore Cortex-A9 Tile' is... Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Fix two section mismatch warnings in the platform SMP bringup code for Realview and Versatile Express: WARNING: arch/arm/mach-realview/built-in.o(.text+0x8ac): Section mismatch in reference from the function write_pen_release() to the variable .cpuinit.data:pen_release The function write_pen_release() references the variable __cpuinitdata pen_release. This is often because write_pen_release lacks a __cpuinitdata annotation or the annotation of pen_release is wrong. WARNING: arch/arm/mach-vexpress/built-in.o(.text+0x7b4): Section mismatch in reference from the function write_pen_release() to the variable .cpuinit.data:pen_release The function write_pen_release() references the variable __cpuinitdata pen_release. This is often because write_pen_release lacks a __cpuinitdata annotation or the annotation of pen_release is wrong. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 21 1月, 2011 1 次提交
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由 David Rientjes 提交于
The meaning of CONFIG_EMBEDDED has long since been obsoleted; the option is used to configure any non-standard kernel with a much larger scope than only small devices. This patch renames the option to CONFIG_EXPERT in init/Kconfig and fixes references to the option throughout the kernel. A new CONFIG_EMBEDDED option is added that automatically selects CONFIG_EXPERT when enabled and can be used in the future to isolate options that should only be considered for embedded systems (RISC architectures, SLOB, etc). Calling the option "EXPERT" more accurately represents its intention: only expert users who understand the impact of the configuration changes they are making should enable it. Reviewed-by: NIngo Molnar <mingo@elte.hu> Acked-by: NDavid Woodhouse <david.woodhouse@intel.com> Signed-off-by: NDavid Rientjes <rientjes@google.com> Cc: Greg KH <gregkh@suse.de> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jens Axboe <axboe@kernel.dk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Robin Holt <holt@sgi.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 18 1月, 2011 5 次提交
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由 Jassi Brar 提交于
Signed-off-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jassi Brar 提交于
Signed-off-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jassi Brar 提交于
Signed-off-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jassi Brar 提交于
Signed-off-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Jassi Brar 提交于
Add missing virtual ASoC DMA device. Signed-off-by: NJassi Brar <jassi.brar@samsung.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com> [kgene.kim@samsung.com: minor changed title] Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 15 1月, 2011 16 次提交
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由 Russell King 提交于
When DEBUG_LL is not set, we don't want __error_a re-entering __lookup_machine_type - we want it to go to the error function. This used to be the case before we reorganized the layout for hotplug cpu, as we used to fall through to __error. With the changed layout, we need an explicit branch here instead. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Eric Miao 提交于
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Philip Rakity 提交于
Drive strength for PXA910 is a 2 bit value but because of the mapping in plat-pxa/mfp.h needs to be shifted up one bit to handle real location in mfp registers. (MMP2 and PXA910 drive strength start at bit 11 while PXA168 starts at bit 10). Values 0, 1, 2, and 3 effectively need to be 0, 2, 4, and 6 to fit into register. 8 does not work. Signed-off-by: NPhilip Rakity <prakity@marvell.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Philip Rakity 提交于
Drive strength for MMP2 is a 2 bit value but because of the mapping in plat-pxa/mfp.h needs to be shifted up one bit to handle real location in mfp registers. (MMP2 and PXA910 drive strength start at bit 11 while PXA168 starts at bit 10). Values 0, 1, 2, and 3 effectively need to be 0, 2, 4, and 6 to fit into register. 8 does not work. Signed-off-by: NPhilip Rakity <prakity@marvell.com> Tested-by: NJohn Watlington <wad@laptop.org> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Eric Miao 提交于
Signed-off-by: NEric Miao <eric.y.miao@gmail.com> Tested-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Russell King 提交于
Rabin Vincent reports: | On SMP, this BUG() in save_stack_trace_tsk() can be easily triggered | from user space by reading /proc/$PID/stack, where $PID is any pid but | the current process: | | if (tsk != current) { | #ifdef CONFIG_SMP | /* | * What guarantees do we have here that 'tsk' | * is not running on another CPU? | */ | BUG(); | #else Fix this by replacing the BUG() with an entry to terminate the stack trace, returning an empty trace - I'd rather not expose the dwarf unwinder to a volatile stack of a running thread. Reported-by: NRabin Vincent <rabin@rab.in> Tested-by: NRabin Vincent <rabin@rab.in> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Build errors similar this appeared in todays kautobuild for the above targets: In file included from arch/arm/include/asm/pgtable.h:461, from arch/arm/mach-pxa/generic.c:26: include/asm-generic/pgtable.h: In function 'ptep_test_and_clear_young': include/asm-generic/pgtable.h:29: error: dereferencing pointer to incomplete type None of the .c files including asm/pgtable.h with this error is using this header, so simply remove the include. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Dima Zavin 提交于
Do not use memory bank info to request the "system ram" resources as they do not track holes created by memblock_remove inside machine's reserve callback. If the removed memory is passed as platform_device's ioresource, then drivers that call request_mem_region would fail due to a conflict with the incorrectly configured system ram resource. Instead, iterate through the regions of memblock.memory and add those as "System RAM" resources. Signed-off-by: NDima Zavin <dima@android.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Igor Plyatov 提交于
The GS_IA18_S (GMS) is a carrier board from GeoSIG Ltd used with the Stamp9G20 SoM from Taskit company. It operate as an internet accelerometer. Signed-off-by: NIgor Plyatov <plyatov@gmail.com> [nicolas.ferre@atmel.com: rm Kconfig, whitespace fixes, change machine name] Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Sergio Tanzilli 提交于
Signed-off-by: NSergio Tanzilli <tanzilli@acmesystems.it> [nicolas.ferre@atmel.com: whitespace fixes, change machine name] Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Jesper Juhl 提交于
Signed-off-by: NJesper Juhl <jj@chaosbits.net> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
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由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Pavel Machek 提交于
Signed-off-by: NPavel Machek <pma@sysgo.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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