GPIO32 is a standard optional extension to the Xtensa architecture
core that provides preconfigured output and input ports for intra
SoC signaling. The GPIO32 option is implemented as 32bit Tensilica
Instruction Extension (TIE) output state called EXPSTATE, and 32bit
input wire called IMPWIRE. This driver treats input and output
states as two distinct devices.

v3:
* Use BUG() in xtensa_impwire_set_value() to indicate that
  it should never be called (Linus Walleij)
v2:
* Address the comments of Linus Walleij:
  - Add a few comments
  - Expand commit log message
  - Use the BIT() macro for bit offsets
  - Rewrite CPENABLE handling as static inlines
  - Use device_initcall()
* Depend on !SMP for reason explained in the comments (Marc Gauthier)
* Use XCHAL_CP_ID_XTIOP to enable/disable GPIO32 only
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add GPIO driver for MOXA ART SoCs.
Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The GPIO driver for the Abilis Systems TB10x series of SOCs based on ARC700
CPUs. It supports GPIO control and GPIO interrupt generation. This driver
works in conjunction with the TB10x pinctrl driver.
Signed-off-by: NSascha Leuenberger <sascha.leuenberger@abilis.com>
Signed-off-by: NChristian Ruppert <christian.ruppert@abilis.com>
Acked-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

gpio-langwell is a deprecated name. Despite the driver was made
initially for Langwell, it supports now other Intel Mid SoC's.

This patch does no change beside the file renaming with Kconfig/Makefile
update.
Signed-off-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Move the IOP GPIO driver to live with its siblings in the
GPIO subsystem.

Cc: Lennert Buytenhek <kernel@wantstofly.org>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Mikael Pettersson <mikpe@it.uu.se>
Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the GPIO driver for the Broadcom bcm281xx family of mobile SoCs.
These GPIO controllers may contain up to 8 banks where each bank
includes 32 pins that can be driven high or low and act as an edge
sensitive interrupt.
Signed-off-by: NMarkus Mayer <markus.mayer@linaro.org>
Reviewed-by: NChristian Daudt <csd@broadcom.com>
Reviewed-by: NTim Kryger <tim.kryger@linaro.org>
Reviewed-by: NMatt Porter <matt.porter@linaro.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
[Added depends on OF_GPIO]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds support for the GPIOs found on the Fintek super-I/O
chips F71882FG and F71889F.

A super-I/O is a legacy I/O controller embedded on x86 motherboards. It
is used to connect the low-bandwidth devices. Among others functions the
F71882FG/F71889F provides: a parallel port, two serial ports, a keyboard
controller, an hardware monitoring controller and some GPIO pins.

Note that this super-I/Os are embedded on some Atom-based LaCie NASes.
The GPIOs are used to control the LEDs and the hard drive power.

Changes since v3:
- Use request_muxed_region to protect the I/O ports against concurrent
  accesses.

Changes since v2:
- Remove useless NULL setters for driver data.

Changes since v1:
- Enhance the commit message by describing what is a Super-I/O.
- Use self-explanatory names for the GPIO register macros.
- Add a comment to explain the platform device and driver registration.
- Fix gpio_get when GPIO is configured in input mode. I only had
  the hardware to check this mode recently...
Signed-off-by: NSimon Guinot <simon.guinot@sequanux.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
GPIO pins, this driver handles them all.  Configuring the pins as
interrupt sources is handled elsewhere (OCTEON's irq handling code).
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/5633/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add gpio support for the on-board PLD found on some Kontron embedded modules.

Originally-from: Michael Brunner <michael.brunner@kontron.com>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NKevin Strasser <kevin.strasser@linux.intel.com>
Acked-by: NDarren Hart <dvhart@linux.intel.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a GPIO driver for the low-power Powerdown Controller GPIOs in the
TZ1090 SoC.

The driver is instantiated by device tree and supports interrupts for
the SysWake GPIOs only.

Changes in v4:
 - fix typos in DT bindings compatible properties
 - reference Documentation/devicetree/bindings/gpio/gpio.txt in
   gpio-ranges description in DT bindings
 - fix gpio-ranges examples in DT bindings (it must now have 3 cells)

Changes in v3:
 - separated from irq-imgpdc and removed arch/metag changes to allow
   these patches to go upstream separately via the pinctrl[/gpio] trees
   (particularly the pinctrl drivers depend on the new pinconf DT
   bindings).
 - some s/unsigned/unsigned int/.
 - gpio-tz1090*: refer to <dt-bindings/gpio/gpio.h> and
   <dt-bindings/interrupt-controller/irq.h> flags in bindings.
 - gpio-tz1090*: move initcall from postcore to subsys.

Changes in v2:
 - gpio-tz1090-pdc: remove references to Linux flags in dt bindings
 - gpio-tz1090-pdc: make use of BIT() from linux/bitops.h
 - gpio-tz1090-pdc: make register accessors inline to match pinctrl
 - gpio-tz1090-pdc: update gpio-ranges to use 3 cells after recent ABI
   breakage
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a GPIO driver for the main GPIOs found in the TZ1090 (Comet) SoC.
This doesn't include low-power GPIOs as they're controlled separately
via the Powerdown Controller (PDC) registers.

The driver is instantiated by device tree and supports interrupts for
all GPIOs.

Changes in v4:
 - fix typos in DT bindings compatible properties
 - reference Documentation/devicetree/bindings/gpio/gpio.txt in
   gpio-ranges description in DT bindings
 - fix gpio-ranges examples in DT bindings (it must now have 3 cells)
 - gpio-tz1090: use of_property_read_u32 instead of of_get_property

Changes in v3:
 - separated from irq-imgpdc and removed arch/metag changes to allow
   these patches to go upstream separately via the pinctrl[/gpio] trees
   (particularly the pinctrl drivers depend on the new pinconf DT
   bindings).
 - some s/unsigned/unsigned int/.
 - some s/unsigned int/bool/ and use of BIT().
 - gpio-tz1090*: refer to <dt-bindings/gpio/gpio.h> and
   <dt-bindings/interrupt-controller/irq.h> flags in bindings.
 - gpio-tz1090*: move initcall from postcore to subsys.
 - gpio-tz1090: add REG_ prefix to some constants for consistency.
 - gpio-tz1090: add comment to explain tz1090_gpio_irq_next_edge
   cunningness.

Changes in v2:
 - gpio-tz1090: remove references to Linux flags in dt bindings
 - gpio-tz1090: make use of BIT() from linux/bitops.h
 - gpio-tz1090: make register accessors inline to match pinctrl
 - gpio-tz1090: update gpio-ranges to use 3 cells after recent ABI
   breakage
Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds Kconfig entry that selects whether legacy Samsung GPIO
driver should be built or not. For platforms that support only DT based
boot, the new pinctrl driver is used and so the old one is not needed.

Cc: Grant Likely <grant.likely@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This reverts commit bd51de53.

Turns out that multiplatform breaks some uses cases, such as when you
have an existing defconfig, since it adds the new EXYNOS_SINGLE config
option as a dependecy. As a result, nearly all exynos config options
will be disabled by default.

Reverting instead of rebasing since this branch is pulled in as a
dependency elsewhere.
Signed-off-by: NOlof Johansson <olof@lixom.net>

This driver supports GRGPIO gpio cores available in the GRLIB VHDL IP
core library from Aeroflex Gaisler.
Signed-off-by: NAndreas Larsson <andreas@gaisler.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This makes it possible to enable the exynos platform as part of a
multiplatform kernel, in addition to keeping the single-platform
exynos support.

The multiplatform variant has a number of limitations at the moment:

* It only supports DT-enabled machines. This is not a problem in
  the long run, as non-DT machines for exynos are going away.
  The main problem here is that the gpio code and the exynos_eint
  irqchip are not multiplatform capable but still required for
  ATAGS based boot.
* The watchdog driver is still missing a conversion.
* sparsemem and memory_holes are currently not supported in
  multiplatform.

The the multiplatform aware ARCH_EXYNOS Kconfig symbol is disabled
for now, as dependent patches are still pending in other
subsystem trees. We will enable it once everything comes together.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

With the move to a combined pinctrl/gpio driver, the arch-vt8500
gpio driver is no longer required.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

This patch is V3 of a GPIO driver for the R-Car series of
SoCs from Renesas. This driver is designed to be reusable
between multiple SoCs that share the same basic building block,
but so far it has only been used on R-Car H1 (r8a7779).

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on a single I/O memory
range and the 32 GPIOs are hooked up a single interrupt.

In the case of R-Car H1 either external IRQ pins or GPIOs
with interrupts can be used for on-board interupts. For
external IRQs 4 pins are supported, and in the case of GPIO
there are 202 GPIOS as 202 interrupts hooked up via 6 driver
instances and to the GIC and the Cortex-A9 Quad.

At this point this driver is interfacing as a regular
platform device driver. In the future DT support will be
submitted as an incremental feature patch.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add gpio driver for TI Palmas series PMIC. This has 8 gpio which can
work as input/output.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

Add gpio support for Intel Lynxpoint chipset.

Lynxpoint supports 94 gpio pins which can generate interrupts.
Driver will fail requests for pins that are marked as owned by ACPI, or
set in an alternate mode (non-gpio).
Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The AB8500 GPIO driver has been marked BROKEN for ages, and we
have something better in store: a shiny new pinctrl driver. So
let use delete this old driver as the first step.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Some architectures (e.g. blackfin) provide gpio API without requiring
GPIOLIB support (ARCH_WANT_OPTIONAL_GPIOLIB).  devm_gpio_* functions
should also work for these architectures, since they do not really
depend on GPIOLIB.

Add a new option GPIO_DEVRES (enabled by default) to control the build
of devres.c.  It also removes the empty version of devm_gpio_*
functions for !GENERIC_GPIO build from linux/gpio.h, and moves the
function declarations from asm-generic/gpio.h into linux/gpio.h.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Technologic Systems TS-5500 provides digital I/O lines exposed through
pin blocks. On this platform, there are three of them, named DIO1, DIO2
and LCD port, that may be used as a DIO block.

The TS-5500 pin blocks are described in the product's wiki:
http://wiki.embeddedarm.com/wiki/TS-5500#Digital_I.2FO

This driver is not limited to the TS-5500 blocks. It can be extended to
support similar boards pin blocks, such as on the TS-5600.

This patch is the V2 of the previous https://lkml.org/lkml/2012/9/25/671
with corrections suggested by Linus Walleij.
Signed-off-by: NVivien Didelot <vivien.didelot@savoirfairelinux.com>
Signed-off-by: NJerome Oufella <jerome.oufella@savoirfairelinux.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add support for translating ACPI GPIO pin numbers to Linux GPIO API pins.
Needs a gpio controller driver with the acpi handler hook set.

Drivers can use acpi_get_gpio() to translate ACPI5 GpioIO and GpioInt
resources to Linux GPIO's.
Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

This adds the mfd cell to use the gpio a and gpio b part
of the Nano River Technologies viperboard.
Signed-off-by: NLars Poeschel <poeschel@lemonage.de>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

SPEAr platform provides a provision to control chipselects of ARM PL022
Prime Cell spi controller through its system registers, which otherwise
remains under PL022 control which some protocols do not want.

This commit intends to provide the spi chipselect control in software over
gpiolib interface. spi chip drivers can use the exported gpiolib interface to
define their chipselect through DT or platform data.

Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: NVipin Kumar <vipin.kumar@st.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The CLPS711X CPUs provide some GPIOs for use in the system. This
driver provides support for these via gpiolib. Due to platform
limitations, driver does not support interrupts, only inputs and
outputs.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This is the GPIO patch for the DA9055 PMIC. This patch has got
dependency on the DA9055 MFD core.

This patch is functionally tested on SMDK6410 board.
Signed-off-by: NDavid Dajun Chen <dchen@diasemi.com>
Signed-off-by: NAshish Jangam <ashish.jangam@kpitcummins.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This driver aims at replacing the arch/arm/plat-orion/gpio.c driver,
and is designed to be compatible with all Marvell EBU SoCs: Orion,
Kirkwood, Dove, Armada 370/XP and Discovery.

It has been successfully tested on Dove and Armada XP at the moment.

Compared to the plat-orion driver, this new driver has the following
added benefits:

 *) Support for Armada 370 and Armada XP
 *) It is integrated with the mvebu pinctrl driver so that GPIO pins
    are properly muxed, and the GPIO driver knows which GPIO pins are
    output-only or input-only.
 *) Properly placed in drivers/gpio
 *) More extensible mechanism to support platform differences. The
    plat-orion driver uses a simple mask-offset DT property, which
    works fine for Discovery MV78200 but not for Armada XP. The new
    driver uses different compatible strings to identify the different
    variants of the GPIO controllers.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Tested-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Converted the existing arch-vt8500 gpio to a platform_device.
Added support for WM8505 and WM8650 GPIO controllers.
Replaced existing readl/writel calls with _relaxed variants.
Replaced existing unsigned variables with u32 to match register size.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

TWL6040 provides GPO lines to be used for controlling external devices.The number
of lines different between versions: twl6040 have 3 GPO while TWL6041 have 1.
Signed-off-by: NSergio Aguirre <saaguirre@ti.com>
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

This commit adds a driver for the Avionic Design N-bit GPIO expander.
The expander provides a variable number of GPIO pins with interrupt
support.

Changes in v2:
- allow building the driver as a module
- assign of_node unconditionally
- use linear mapping IRQ domain
- properly cleanup IRQ domain
- add OF device table and annotate device tables
- emulate rising and falling edge triggers
- increase #gpio-cells to 2
- drop support for !OF
- use IS_ENABLED to conditionalize DEBUG_FS code

Changes in v3:
- make IRQ support runtime configurable (interrupt-controller property)
- drop interrupt-controller and #interrupt-cells from DT binding
- add inline to_adnp() function to wrap container_of() macro
- consistently use adnp as name for struct adnp variables
- remove irq_mask_cur and rename irq_mask to irq_enable
- fix a subtle deadlock in adnp_gpio_direction_output()
- remove dynamic allocations from debugfs code
- rename regs to num_regs to avoid confusion
- annotate non-trivial code with comments
- don't acquire mutex in adnp_gpio_get()
- assume NO_IRQ == 0

Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: linux-kernel@vger.kernel.org
Acked-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Converting the gpio driver of tps6586x to a platform
driver in place of registering the gpio through core
driver.
The motivation of the change is:
- This is inline with the mfd drivers implementation.
- This will move the related gpio support to gpio driver
  folder where all gpio related drivers are available.
  This will be easy the maintenance and enhancement is
  anything done for gpio.
- The gpio functionality can be selected through config
  variable.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

The Arizona class devices provide some GPIOs for use in the system. This
driver provides support for these via gpiolib. Currently interrupts are
not supported, normally the GPIOs are outputs only.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
[Fold in WM5110 support patch]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add a driver to use GPIO pins available on several AMD south bridges
(currently only AMD 8111 is supported).
Signed-off-by: NDmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Move the 2 drivers from arch/mips/lantiq/xway/ to the subsystem and make them
buildable.

The following 2 patches will convert the drivers to OF.
Signed-off-by: NJohn Crispin <blogic@openwrt.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Patchwork: https://patchwork.linux-mips.org/patch/3838/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The PMIC device RC5T583 from RICOH supports 8 gpios.
Adding gpio driver for this device to access the pins
control through gpio library.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
[grant.likely: slight cosmetic changes]
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch is V2 of the Emma Mobile GPIO driver. This
driver is designed to be reusable between multiple SoCs
that share the same basic building block, but so far it
has only been used on Emma Mobile EV2.

Each driver instance handles 32 GPIOs with individually
maskable IRQs. The driver operates on two I/O memory
ranges and the 32 GPIOs are hooked up to two interrupts.

In the case of Emma Mobile EV2 this GPIO building block
is used as main external interrupt controller hooking up
159 GPIOS as 159 interrupts via 5 driver instances and
10 interrupts to the GIC and the Cortex-A9 Dual.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>

Add gpio support for Intel MSIC chips found in Intel Medfield platforms.
MSIC supports totally 24 GPIOs with 16 low voltage and 8 high voltage pins.
Driver uses MSIC mfd interface for MSIC access.

(Updated comment to indicate why locking is actually safe)
Signed-off-by: NMathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

I'm moving this driver over to the pinctrl subsystem to convert
the custom pin mux/config scheme over to use pinctrl.
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This introduces 128 gpio bits (for each PCI device installed) with
working interrupt support.
Signed-off-by: NAlessandro Rubini <rubini@gnudd.com>
Acked-by: NGiancarlo Asnaghi <giancarlo.asnaghi@st.com>
Cc: Alan Cox <alan@linux.intel.com>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>