1. 03 6月, 2011 2 次提交
  2. 26 5月, 2011 1 次提交
  3. 25 5月, 2011 1 次提交
    • M
      bitmap, irq: add smp_affinity_list interface to /proc/irq · 4b060420
      Mike Travis 提交于
      Manually adjusting the smp_affinity for IRQ's becomes unwieldy when the
      cpu count is large.
      
      Setting smp affinity to cpus 256 to 263 would be:
      
      	echo 000000ff,00000000,00000000,00000000,00000000,00000000,00000000,00000000 > smp_affinity
      
      instead of:
      
      	echo 256-263 > smp_affinity_list
      
      Think about what it looks like for cpus around say, 4088 to 4095.
      
      We already have many alternate "list" interfaces:
      
      /sys/devices/system/cpu/cpuX/indexY/shared_cpu_list
      /sys/devices/system/cpu/cpuX/topology/thread_siblings_list
      /sys/devices/system/cpu/cpuX/topology/core_siblings_list
      /sys/devices/system/node/nodeX/cpulist
      /sys/devices/pci***/***/local_cpulist
      
      Add a companion interface, smp_affinity_list to use cpu lists instead of
      cpu maps.  This conforms to other companion interfaces where both a map
      and a list interface exists.
      
      This required adding a bitmap_parselist_user() function in a manner
      similar to the bitmap_parse_user() function.
      
      [akpm@linux-foundation.org: make __bitmap_parselist() static]
      Signed-off-by: NMike Travis <travis@sgi.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jack Steiner <steiner@sgi.com>
      Cc: Lee Schermerhorn <lee.schermerhorn@hp.com>
      Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      4b060420
  4. 18 5月, 2011 3 次提交
  5. 03 5月, 2011 2 次提交
  6. 23 4月, 2011 3 次提交
  7. 03 4月, 2011 1 次提交
  8. 31 3月, 2011 1 次提交
  9. 30 3月, 2011 3 次提交
  10. 29 3月, 2011 7 次提交
  11. 28 3月, 2011 3 次提交
  12. 27 3月, 2011 5 次提交
  13. 26 3月, 2011 1 次提交
  14. 24 3月, 2011 1 次提交
  15. 17 3月, 2011 2 次提交
  16. 12 3月, 2011 1 次提交
    • T
      genirq: Add chip flag to force mask on suspend · d209a699
      Thomas Gleixner 提交于
      On suspend we disable all interrupts in the core code, but this does
      not mask the interrupt line in the default implementation as we use a
      lazy disable approach. That means we mark the interrupt disabled, but
      leave the hardware unmasked. That's an optimization because we avoid
      the hardware access for the common case where no interrupt happens
      after we marked it disabled. If an interrupt happens, then the
      interrupt flow handler masks the line at the hardware level and marks
      it pending.
      
      Suspend makes use of this delayed disable as it "disables" all
      interrupts when preparing the suspend transition. Right before the
      system goes into hardware suspend state it checks whether one of the
      interrupts which is marked as a wakeup interrupt came in after
      disabling it.
      
      Most interrupt chips have a separate register which selects the
      interrupts which can wake up the system from suspend, so we don't have
      to mask any on the non wakeup interrupts.
      
      But now we have to deal with brilliant designed hardware which lacks
      such a wakeup configuration facility. For such hardware it's necessary
      to mask all non wakeup interrupts before going into suspend in order
      to avoid the wakeup from random interrupts.
      
      Rather than working around this in the affected interrupt chip
      implementations we can solve this elegant in the core code itself.
      
      Add a flag IRQCHIP_MASK_ON_SUSPEND which can be set by the irq chip
      implementation to indicate, that the interrupts which are not selected
      as wakeup sources must be masked in the suspend path. Mask them in the
      loop which checks the wakeup interrupts pending flag.
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Reviewed-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org>
      LKML-Reference: <alpine.LFD.2.00.1103112112310.2787@localhost6.localdomain6>
      d209a699
  17. 09 3月, 2011 1 次提交
  18. 02 3月, 2011 1 次提交
  19. 26 2月, 2011 1 次提交
    • T
      genirq: Provide forced interrupt threading · 8d32a307
      Thomas Gleixner 提交于
      Add a commandline parameter "threadirqs" which forces all interrupts except
      those marked IRQF_NO_THREAD to run threaded. That's mostly a debug option to
      allow retrieving better debug data from crashing interrupt handlers. If
      "threadirqs" is not enabled on the kernel command line, then there is no
      impact in the interrupt hotpath.
      
      Architecture code needs to select CONFIG_IRQ_FORCED_THREADING after
      marking the interrupts which cant be threaded IRQF_NO_THREAD. All
      interrupts which have IRQF_TIMER set are implict marked
      IRQF_NO_THREAD. Also all PER_CPU interrupts are excluded.
      
      Forced threading hard interrupts also forces all soft interrupt
      handling into thread context.
      
      When enabled it might slow down things a bit, but for debugging problems in
      interrupt code it's a reasonable penalty as it does not immediately
      crash and burn the machine when an interrupt handler is buggy.
      
      Some test results on a Core2Duo machine:
      
      Cache cold run of:
       # time git grep irq_desc
      
            non-threaded       threaded
       real 1m18.741s          1m19.061s
       user 0m1.874s           0m1.757s
       sys  0m5.843s           0m5.427s
      
       # iperf -c server
      non-threaded
      [  3]  0.0-10.0 sec  1.09 GBytes   933 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   934 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   933 Mbits/sec
      threaded
      [  3]  0.0-10.0 sec  1.09 GBytes   939 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   934 Mbits/sec
      [  3]  0.0-10.0 sec  1.09 GBytes   937 Mbits/sec
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      LKML-Reference: <20110223234956.772668648@linutronix.de>
      8d32a307