If you're pushing a plane hard (i.e. you need most or all of the FIFO
entries just to cover your frame refresh latency), the watermark level
may end up being negative.  So fix up the signed vs. unsigned math in
the calculation function to handle this correctly, giving all available
FIFO entries to such a configuration.
Reported-by: NEric Anholt <eric@anholt.net>
Tested-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

I discovered several bugs in the FIFO code that was recently applied.
Some of them fell into the "how did this ever work" category, since in
some cases we were using the wrong FIFO size values, and the
calculations ended up being way off.

This patch fixes all the bugs I found, and works well on my GM45, 915GM
and 855GM test machines; but as usual with these sorts of patches
broader testing is definitely requested (in particular this patch
affects 830, 845 and 865 for which I don't have test hardware).

Overall, the patch clarifies the watermark calculation function by
adding some comments and debug info, and making the variable names a
bit clearer.  The "get FIFO size" portion of the code has also been
corrected, so we should be able to properly detect the FIFO allocations
for each pipe, for use in the watermark calculation.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

The 915 and 945 scanout engines can handle frame buffers up to 4096 pixels
wide. Pre-9xx hardware has an 8192 byte stride limit, and so we leave the
existing 2048 max in place.

I'm not sure why we limit the height to the same value; there's no intrinsic
hardware limit in the scanout engine.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Vbios will set lvds register correctly based on
current algorithm for lingle/dual Channel LVDS when
system boot, so we can accept this configuration
directly, regardless of LVDS enable status.

It fixed freedesktop.org bug #22262
Signed-off-by: NFlorian Mickler <florian@mickler.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

For some reason, the DP clocks were based off a 100MHz reference instead of
the standard 96MHz reference. This caused some DP monitors to fail to lock
to the signal.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

We are seeing compilation failures on i386 in some environments due
to an undefined reference as below:

    ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!

This is generated due to a raw 64 bit divide in the i915 driver.  Fix up
this raw divide.
Signed-off-by: NAndy Whitcroft <apw@canonical.com>
Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

This patch from jbarnes and myself adds FIFO watermark control to the
driver.  This is needed for both power saving features on new platforms
with the so-called "big FIFO" and for controlling FIFO allocation
between pipes in multi-head configurations.

It's also necessary infrastructure to support things like framebuffer
compression and configuration supportability checks (i.e. checking a
configuration against available bandwidth).
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NShaohua Li <shaohua.li@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

The array of DAC limits was only ever referenced with #defined constant
offsets, and keeping those #define values in sync with the array itself was a
nuisance. This will make future changes to the set of DAC limits less
error-prone.
Signed-off-by: NKeith Packard <keithp@keithp.com>

Signed-off-by: NKeith Packard <keithp@keithp.com>

With the work by Jesse Barnes to eliminate allocation of fences during
execbuffer, it becomes possible to write to the scan-out buffer with it
never acquiring a fence (simply by only ever writing to the object using
tiled GPU commands and never writing to it via the GTT). So for pre-i965
chipsets which require fenced access for tiled scan-out buffers, we need
to obtain a fence register.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NEric Anholt <eric@anholt.net>

duplicate the mode into fbcon storage, so when we free modes later
we don't just lose this.
Signed-off-by: NDave Airlie <airlied@redhat.com>

With the DRM-driven DPMS code, encoders are considered idle unless a
connector is hooked to them, so mode setting is skipped. This makes load
detection fail as none of the hardware is enabled.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Ensure that the drm_vblank_pre_modeset() is always balanced by
drm_vblank_post_modeset() within intel_crtc_mode_set().
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NEric Anholt <eric@anholt.net>

We can safely assume that cursor addresses will not extend beyond the
addressable screen dimensions; setting the additional bits is harmless in
any case.
Signed-off-by: NKeith Packard <keithp@keithp.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

This adds kernel mode setting on IGDNG with VGA output support.
Note that suspend/resume doesn't work yet.
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

For some reason we never added 8xx desktop cursor support to the
kernel.  This patch fixes that.

[krh: Also set the size on pre-i915 hw.]
Tested-by: NKristian Høgsberg <krh@redhat.com>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

This allows userlevel code to discover the pipe number corresponding
to a given CRTC ID. This is necessary for doing pipe-specific
operations such as waiting for vblank on a given CRTC.  Failure to use
the right pipe mapping can result in GPU hangs, or at least failure
to actually sync to vblank.
Signed-off-by: NCarl Worth <cworth@cworth.org>
[anholt: Style touchups from review]
Signed-off-by: NEric Anholt <eric@anholt.net>

This patch corrects a pretty big oversight in the KMS code for 965+
chips.  The current code is missing tiled surface register programming,
so userland can allocate a tiled surface and use it for mode setting,
resulting in corruption.  This patch fixes that, allowing for tiled
front buffers on 965+.

Cc: stable@kernel.org
Tested-by: NArkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>

Signed-off-by: NShaohua Li <shaohua.li@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

This brings SDVO TV support from 2D driver, including origin
fix f1ca56e17d0 and later fix 2fcf4fcccfe. Also fix wrong modeline
definitions for SDVO TV.
Signed-off-by: NZhenyu Wang <zhenyu.z.wang@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

udelay() of 20 milliseconds really ought to just use mdelay(), that avoids
the various wrap scenarios and also is more readable
Signed-off-by: NArjan van de Ven <arjan@linux.intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

This is a G33-like desktop and mobile chipset.
Signed-off-by: NShaohua Li <shaohua.li@intel.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

This fixes incorrect detection of the second SDVO/HDMI output on G4X, and
extra boot time on pre-G4X.
Signed-off-by: NKristian Høgsberg <krh@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>

This improves the PLL timings according to the suggestion of the hardware
engineers.  This results in some outputs being able to sync that weren't
able to before.

This is part of fixing fd.o bug #17508.
Signed-off-by: NMa Ling <ling.ma@intel.com>
[anholt: cleaned up a couple of redundant comments]
Signed-off-by: NEric Anholt <eric@anholt.net>

The values come from the internal reference spreadsheet on PLL
timing limits for the G4X chipsets.

Part of fixing fd.o bug #17508
Signed-off-by: NMa Ling <ling.ma@intel.com>
[anholt: Cleaned up some whitespace]
Signed-off-by: NEric Anholt <eric@anholt.net>

These are normal; we walk through different values looking for the right
one, so why flood the screen with messages?
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@linux.ie>

there might be a nicer way to fix this but this is the simplest for now.
Signed-off-by: NPierre Willenbrock <pierre@pirsoft.de>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Need to do this in case the unref ends up doing a free.
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Lifted from the DDX modesetting.
Signed-off-by: NKristian Høgsberg <krh@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@redhat.com>

They used to be different.  Now they're identical.
Signed-off-by: NKristian Høgsberg <krh@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Signed-off-by: NKristian Høgsberg <krh@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@redhat.com>

We need to hold the struct_mutex around pinning and the phys object
operations.
Signed-off-by: NKristian Høgsberg <krh@redhat.com>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@redhat.com>

Check the error paths within intel_pipe_set_base() to first cleanup and
then report back the error.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@linux.ie>

Set the request alignment to 0, and leave it up to i915_gem_object_pin()
to set the appropriate alignment to match the fence covering the object.

Eric Anholt mentioned that the pinning code is meant to choose the
maximum of the request alignment and that of the fence covering the
object... However currently, the pinning code will only apply the fence
constraints if the supplied alignment is 0.
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@linux.ie>

Pull in an update from the 2D driver (hopefully the last one, future work
should be done here and pulled back into xf86-video-intel as needed).
Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NDave Airlie <airlied@linux.ie>

This saves startup time from probing SDVO, and saves setting up HDMI outputs
on G4X devices that don't have them.
Signed-off-by: NDave Airlie <airlied@linux.ie>

This makes sure the mutex is held around the unreference.
Signed-off-by: NDave Airlie <airlied@redhat.com>

This is an initial patch to do support for objects which needs physical
contiguous main ram, cursors and overlay registers on older chipsets.

These objects are bound on cursor bin, like pinning, and we copy
the data to/from the backing store object into the real one on attach/detach.

notes:
possible over the top in attach/detach operations.
no overlay support yet.
Signed-off-by: NDave Airlie <airlied@redhat.com>