1. 15 1月, 2015 1 次提交
  2. 27 11月, 2014 1 次提交
  3. 11 11月, 2014 2 次提交
  4. 10 11月, 2014 1 次提交
  5. 03 10月, 2014 1 次提交
    • D
      ASoC: tlv320aic3x: fix PLL D configuration · 31d9f8fa
      Dmitry Lavnikevich 提交于
      Current caching implementation during regcache_sync() call bypasses
      all register writes of values that are already known as default
      (regmap reg_defaults). Same time in TLV320AIC3x codecs register 5
      (AIC3X_PLL_PROGC_REG) write should be immediately followed by register
      6 write (AIC3X_PLL_PROGD_REG) even if it was not changed. Otherwise
      both registers will not be written.
      
      This brings to issue that appears particulary in case of 44.1kHz
      playback with 19.2MHz master clock. In this case AIC3X_PLL_PROGC_REG
      is 0x6e while AIC3X_PLL_PROGD_REG is 0x0 (same as register
      default). Thus AIC3X_PLL_PROGC_REG also remains not written and we get
      wrong playback speed.
      
      In this patch snd_soc_read() is used to get cached pll values and
      snd_soc_write() (unlike regcache_sync() this function doesn't bypasses
      hardware default values) to write them to registers.
      Signed-off-by: NDmitry Lavnikevich <d.lavnikevich@sam-solutions.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      Cc: stable@vger.kernel.org
      31d9f8fa
  6. 04 9月, 2014 1 次提交
  7. 01 8月, 2014 1 次提交
  8. 30 6月, 2014 2 次提交
  9. 27 6月, 2014 1 次提交
  10. 01 6月, 2014 1 次提交
  11. 15 4月, 2014 1 次提交
  12. 11 3月, 2014 1 次提交
  13. 10 12月, 2013 1 次提交
  14. 17 10月, 2013 1 次提交
  15. 07 10月, 2013 1 次提交
  16. 25 9月, 2013 6 次提交
  17. 30 7月, 2013 1 次提交
  18. 24 7月, 2013 1 次提交
  19. 16 7月, 2013 2 次提交
  20. 20 6月, 2013 1 次提交
  21. 08 6月, 2013 1 次提交
  22. 05 2月, 2013 1 次提交
    • H
      ASoC: tlv320aic3x: Convert mic bias to a supply widget · e2e8bfdf
      Hebbar Gururaja 提交于
      Convert MicBias widgets to supply widget.
      
      On tlv320aic3x, Mic bias power on/off shares the same register bits
      with output mic bias voltage.  So, when power on mic bias, we need
      reclaim it to voltage value.
      
      Provide a new platform data so that the micbias voltage can be sent
      according to board requirement. Now since tlv320aic3x codec driver
      is DT aware, update dt files and functions to handle this new
      "micbias-vg"  platform data.
      
      Because of sharing of bits, when enabling the micbias, voltage also
      needs to be updated. So use SND_SOC_DAPM_POST_PMU & SND_SOC_DAPM_PRE_PMD
      macro to create an event to handle this.
      
      Since micbias is converted to supply widget, updated machine drivers as
      well.
      
      This change is runtime tested on da850-evm with audio loopback
      (arecord|aplay) for confirmation.
      Signed-off-by: NHebbar Gururaja <gururaja.hebbar@ti.com>
      Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      e2e8bfdf
  23. 30 1月, 2013 1 次提交
  24. 28 8月, 2012 1 次提交
  25. 06 8月, 2012 1 次提交
  26. 10 7月, 2012 3 次提交
  27. 04 7月, 2012 1 次提交
  28. 29 6月, 2012 1 次提交
    • H
      ASoC: tlv320aic3x: Fix codec pll configure bug · c9fe573a
      Hebbar, Gururaja 提交于
      In sound/soc/codecs/tlv320aic3x.c
      
              data = snd_soc_read(codec, AIC3X_PLL_PROGA_REG);
              snd_soc_write(codec, AIC3X_PLL_PROGA_REG,
                            data | (pll_p << PLLP_SHIFT));
      
      In the above code, pll-p value is OR'ed with previous value without
      clearing it. Bug is not seen if pll-p value doesn't change across
      Sampling frequency.
      
      However on some platforms (like AM335x EVM-SK), pll-p may have different
      values across different sampling frequencies. In such case, above code
      configures the pll with a wrong value.
      Because of this bug, when a audio stream is played with pll value
      different from previous stream, audio is heard as differently(like its
      stretched).
      Signed-off-by: NHebbar, Gururaja <gururaja.hebbar@ti.com>
      Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
      Cc: stable@vger.kernel.org
      c9fe573a
  29. 03 6月, 2012 1 次提交
  30. 15 5月, 2012 1 次提交