1. 15 10月, 2009 1 次提交
  2. 09 10月, 2009 1 次提交
  3. 05 10月, 2009 1 次提交
  4. 21 9月, 2009 1 次提交
  5. 04 9月, 2009 3 次提交
  6. 20 8月, 2009 1 次提交
    • P
      ibm_newemac: emac_close() needs to call netif_carrier_off() · d3b325f9
      Petri Gynther 提交于
      When ibm_newemac netdev instance is shutdown with "ifconfig down",
      the netdev interface does not go properly down. netif_carrier_ok()
      keeps returning TRUE even after "ifconfig down".
      
      The problem can be seen when ibm_newemac instances are slaves of
      a bonding interface. The bonding interface code uses netif_carrier_ok()
      to determine the link status of its slaves. When ibm_newemac slave is
      shutdown with "ifconfig down", the bonding interface won't detect any
      link status change because netif_carrier_ok() keeps returning TRUE.
      Signed-off-by: NPetri Gynther <pgynther@google.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d3b325f9
  7. 06 7月, 2009 1 次提交
  8. 13 6月, 2009 1 次提交
  9. 11 4月, 2009 1 次提交
  10. 07 4月, 2009 1 次提交
  11. 22 3月, 2009 1 次提交
  12. 14 3月, 2009 1 次提交
  13. 28 10月, 2008 2 次提交
  14. 21 10月, 2008 1 次提交
  15. 09 10月, 2008 1 次提交
  16. 03 10月, 2008 1 次提交
  17. 30 9月, 2008 1 次提交
  18. 27 8月, 2008 1 次提交
  19. 15 7月, 2008 1 次提交
  20. 09 7月, 2008 1 次提交
    • G
      ibm_newemac: Parameterize EMAC Multicast Match Handling · 05781ccd
      Grant Erickson 提交于
      Various instances of the EMAC core have varying: 1) number of address
      match slots, 2) width of the registers for handling address match slots,
      3) number of registers for handling address match slots and 4) base
      offset for those registers.
      
      As the driver stands today, it assumes that all EMACs have 4 IAHT and
      GAHT 32-bit registers, starting at offset 0x30 from the register base,
      with only 16-bits of each used for a total of 64 match slots.
      
      The 405EX(r) and 460EX now use the EMAC4SYNC core rather than the EMAC4
      core. This core has 8 IAHT and GAHT registers, starting at offset 0x80
      from the register base, with ALL 32-bits of each used for a total of
      256 match slots.
      
      This adds a new compatible device tree entry "emac4sync" and a new,
      related feature flag "EMAC_FTR_EMAC4SYNC" along with a series of macros
      and inlines which supply the appropriate parameterized value based on
      the presence or absence of the EMAC4SYNC feature.
      
      The code has further been reworked where appropriate to use those macros
      and inlines.
      
      In addition, the register size passed to ioremap is now taken from the
      device tree:
      
      	c4 for EMAC4SYNC cores
      	74 for EMAC4 cores
      	70 for EMAC cores
      
      rather than sizeof (emac_regs).
      
      Finally, the device trees have been updated with the appropriate compatible
      entries and resource sizes.
      
      This has been tested on an AMCC Haleakala board such that: 1) inbound
      ICMP requests to 'haleakala.local' via MDNS from both Mac OS X 10.4.11
      and Ubuntu 8.04 systems as well as 2) outbound ICMP requests from
      'haleakala.local' to those same systems in the '.local' domain via MDNS
      now work.
      Signed-off-by: NGrant Erickson <gerickson@nuovations.com>
      Acked-by: NJeff Garzik <jgarzik@pobox.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      05781ccd
  21. 04 7月, 2008 2 次提交
  22. 25 4月, 2008 6 次提交
  23. 29 3月, 2008 1 次提交
  24. 17 3月, 2008 1 次提交
    • P
      NEWEMAC: fix support for pause packets · 4373c932
      Pravin M. Bathija 提交于
      Problem Description and Fix
      ---------------------------
      When a pause packet(with destination as reserved Multicast address) is
      received by the EMAC hardware to control the flow of frames being
      transmitted by it, it is dropped by the hardware unless the reserved
      Multicast address is hashed in to the GAHT[1-4] registers. This code fix
      adds the default reserved multicast address to the GAHT[1-4] registers
      in the EMAC(s) present on the chip. The flow control with Pause packets
      will only work if the following register bits are programmed in EMAC:
      EMACx_MR1[APP] = 1
      EMACx_RMR[BAE] = 1
      EMACx_RMR[MAE] = 1
      
      Behavior that may be observed in a running system
      -------------------------------------------------
      A host transferring data from a PPC based system may send a Pause packet
      to the PPC EMAC requesting it to slow down the flow of packets. If the
      default reserved multicast MAC address is not programmed into the
      GAHT[1-4] registers this Pause packet will be dropped by PPC EMAC and no
      Flow Control will be done.
      Signed-off-by: NPravin M. Bathija <pbathija@amcc.com>
      Signed-off-by: NStefan Roese <sr@denx.de>
      Signed-off-by: NJeff Garzik <jeff@garzik.org>
      4373c932
  25. 29 1月, 2008 1 次提交
  26. 17 1月, 2008 1 次提交
  27. 08 12月, 2007 5 次提交