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  1. 16 10月, 2011 1 次提交
    • B
      e1000e: locking bug introduced by commit 67fd4fcb · a90b412c
      由 Bruce Allan 提交于 
      Commit 67fd4fcb (e1000e: convert to stats64) added the ability to update
statistics more accurately and on-demand through the net_device_ops
.ndo_get_stats64 hook, but introduced a locking bug on 82577/8/9 when
linked at half-duplex (seen on kernels with CONFIG_DEBUG_ATOMIC_SLEEP=y and
CONFIG_PROVE_LOCKING=y).  The commit introduced code paths that caused a
mutex to be locked in atomic contexts, e.g. an rcu_read_lock is held when
irqbalance reads the stats from /sys/class/net/ethX/statistics causing the
mutex to be locked to read the Phy half-duplex statistics registers.

The mutex was originally introduced to prevent concurrent accesses of
resources (the NVM and Phy) shared by the driver, firmware and hardware
a few years back when there was an issue with the NVM getting corrupted.
It was later split into two mutexes - one for the NVM and one for the Phy
when it was determined the NVM, unlike the Phy, should not be protected by
the software/firmware/hardware semaphore (arbitration of which is done in
part with the SWFLAG bit in the EXTCNF_CTRL register).  This latter
semaphore should be sufficient to prevent resource contention of the Phy in
the driver (i.e. the mutex for Phy accesses is not needed), but to be sure
the mutex is replaced with an atomic bit flag which will warn if any
contention is possible.

Also add additional debug output to help determine when the sw/fw/hw
semaphore is owned by the firmware or hardware.
Signed-off-by: NBruce Allan <bruce.w.allan@intel.com>
Reported-by: NFrancois Romieu <romieu@fr.zoreil.com>
Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com>
      a90b412c
  3. 05 10月, 2011 1 次提交
  5. 27 8月, 2011 1 次提交
  7. 19 8月, 2011 1 次提交
  9. 11 8月, 2011 1 次提交
  11. 13 7月, 2011 1 次提交
  13. 12 7月, 2011 1 次提交
  15. 10 6月, 2011 3 次提交
    • B
      e1000e: Clear host wakeup bit on 82577/8 without touching PHY page 800 · 3ebfc7c9
      由 Bruce Allan 提交于 
      The Host Wakeup Active bit in the PHY Port General Configuration register
(page 769 register 17) must be cleared after every PHY reset to prevent an
unexpected wake signal from the PHY. Originally, this was accomplished by
simply reading the PHY Wakeup Control register on page 800 which clears the
Host Wakeup Active bit as a side-effect. Unfortunately, a hardware bug on
the 82577 and 82578 PHY can cause unexpected behavior when registers on
page 800 are accessed while in gigabit mode.

This patch changes the remaining instances when the Host Wakeup Active bit
needs to be cleared while possibly in gigabit mode by accessing the Port
General Configuration register directly instead of accessing any register
on page 800.
Signed-off-by: NBruce Allan <bruce.w.allan@intel.com>
Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      3ebfc7c9
    • B
      e1000e: access multiple PHY registers on same page at the same time · 2b6b168d
      由 Bruce Allan 提交于 
      Doing a PHY page select can take a long time, relatively speaking. This
can cause a significant delay when updating a number of PHY registers on
the same page by unnecessarily setting the page for each PHY access. For
example when going to Sx, all the PHY wakeup registers (WUC, RAR[], MTA[],
SHRAR[], IP4AT[], IP6AT[], etc.) on 82577/8/9 need to be updated which
takes a long time which can cause issues when suspending.

This patch introduces new PHY ops function pointers to allow callers to
set the page directly and do any number of PHY accesses on that page.
This feature is currently only implemented for 82577, 82578 and 82579
PHYs for both the normally addressed registers as well as the special-
case addressing of the PHY wakeup registers on page 800. For the latter
registers, the existing function for accessing the wakeup registers has
been divided up into three- 1) enable access to the wakeup register page,
2) perform the register access and 3) disable access to the wakeup register
page. The two functions that enable/disable access to the wakeup register
page are necessarily available to the caller so that the caller can restore
the value of the Port Control (a.k.a. Wakeup Enable) register after the
wakeup register accesses are done.

All instances of writing to multiple PHY registers on the same page are
updated to use this new method and to acquire any PHY locking mechanism
before setting the page and performing the register accesses, and release
the locking mechanism afterward.

Some affiliated magic number cleanup is done as well.
Signed-off-by: NBruce Allan <bruce.w.allan@intel.com>
Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      2b6b168d
    • B
      e1000e: 82579 intermittently disabled during S0->Sx · 99730e4c
      由 Bruce Allan 提交于 
      When repeatedly cycling Sx->S0 states with the network cable unplugged,
the 82579 PHY may not initialize as expected and may require a full power
cycle to recover functionality to the device.  Workaround this by testing
access of the PHY registers after resuming; if that returns unexpected
results toggle the LANPHYPC signal to power cycle the PHY.

This is implemented in the new function e1000_resume_workarounds_pchlan()
which calls another new function, e1000_toggle_lanphypc_value_ich8lan(),
which has been created to reduce code duplication (same functionality
required by a previous workaround).  Also, e1000e_disable_gig_wol_ich8lan
is now e1000_suspend_workarounds_ich8lan to better reflect what it does.
Signed-off-by: NBruce Allan <bruce.w.allan@intel.com>
Tested-by: NAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
      99730e4c
  17. 27 4月, 2011 1 次提交
  19. 14 4月, 2011 2 次提交
  21. 24 1月, 2011 1 次提交
  23. 14 1月, 2011 1 次提交
  25. 10 1月, 2011 2 次提交
  27. 11 12月, 2010 2 次提交
  29. 29 10月, 2010 1 次提交
  31. 01 10月, 2010 2 次提交
  33. 03 8月, 2010 1 次提交
  35. 24 6月, 2010 1 次提交
  37. 19 6月, 2010 4 次提交
  39. 06 5月, 2010 1 次提交
  41. 28 4月, 2010 1 次提交
  43. 27 3月, 2010 2 次提交
  45. 17 3月, 2010 1 次提交
  47. 05 2月, 2010 1 次提交
  49. 21 1月, 2010 1 次提交
  51. 14 1月, 2010 4 次提交
  53. 03 12月, 2009 1 次提交