1. 07 4月, 2014 9 次提交
    • B
      powerpc/powernv: Add opal_notifier_unregister() and export to modules · 798af00c
      Benjamin Herrenschmidt 提交于
      opal_notifier_register() is missing a pending "unregister" variant
      and should be exposed to modules.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      798af00c
    • B
      powerpc/ppc64: Do not turn AIL (reloc-on interrupts) too early · 8f619b54
      Benjamin Herrenschmidt 提交于
      Turn them on at the same time as we allow MSR_IR/DR in the paca
      kernel MSR, ie, after the MMU has been setup enough to be able
      to handle relocated access to the linear mapping.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8f619b54
    • B
      powerpc/ppc64: Gracefully handle early interrupts · a944a9c4
      Benjamin Herrenschmidt 提交于
      If we take an interrupt such as a trap caused by a BUG_ON before the
      MMU has been setup, the interrupt handlers try to enable virutal mode
      and cause a recursive crash, making the original problem very hard
      to debug.
      
      This fixes it by adjusting the "kernel_msr" value in the PACA so that
      it only has MSR_IR and MSR_DR (translation for instruction and data)
      set after the MMU has been initialized for the processor.
      
      We may still not have a console yet but at least we don't get into
      a recursive fault (and early debug console or memory dump via JTAG
      of the kernel buffer *will* give us the proper error).
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      a944a9c4
    • B
      powerpc/prom: early_init_dt_scan_cpus() updates cpu features only once · 7222f779
      Benjamin Herrenschmidt 提交于
      All our cpu feature updates were done for every CPU in the device-tree,
      thus overwriting the cputable bits over and over again. Instead do them
      only for the boot CPU.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      7222f779
    • B
      powerpc: Make boot_cpuid common between 32 and 64-bit · 36ae37e3
      Benjamin Herrenschmidt 提交于
      Move the definition to setup-common.c and set the init value
      to -1 on both 32 and 64-bit (it was 0 on 64-bit).
      
      Additionally add a check to prom.c to garantee that the init
      value has been udpated after the DT scan.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      36ae37e3
    • B
      powerpc: Adjust CPU_FTR_SMT on all platforms · 4a85b31d
      Benjamin Herrenschmidt 提交于
      For historical reasons that code was under #ifdef CONFIG_PPC_PSERIES
      but it applies equally to all 64-bit platforms.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      4a85b31d
    • M
      powerpc/tm: Disable IRQ in tm_recheckpoint · e6b8fd02
      Michael Neuling 提交于
      We can't take an IRQ when we're about to do a trechkpt as our GPR state is set
      to user GPR values.
      
      We've hit this when running some IBM Java stress tests in the lab resulting in
      the following dump:
      
        cpu 0x3f: Vector: 700 (Program Check) at [c000000007eb3d40]
            pc: c000000000050074: restore_gprs+0xc0/0x148
            lr: 00000000b52a8184
            sp: ac57d360
           msr: 8000000100201030
          current = 0xc00000002c500000
          paca    = 0xc000000007dbfc00     softe: 0     irq_happened: 0x00
            pid   = 34535, comm = Pooled Thread #
        R00 = 00000000b52a8184   R16 = 00000000b3e48fda
        R01 = 00000000ac57d360   R17 = 00000000ade79bd8
        R02 = 00000000ac586930   R18 = 000000000fac9bcc
        R03 = 00000000ade60000   R19 = 00000000ac57f930
        R04 = 00000000f6624918   R20 = 00000000ade79be8
        R05 = 00000000f663f238   R21 = 00000000ac218a54
        R06 = 0000000000000002   R22 = 000000000f956280
        R07 = 0000000000000008   R23 = 000000000000007e
        R08 = 000000000000000a   R24 = 000000000000000c
        R09 = 00000000b6e69160   R25 = 00000000b424cf00
        R10 = 0000000000000181   R26 = 00000000f66256d4
        R11 = 000000000f365ec0   R27 = 00000000b6fdcdd0
        R12 = 00000000f66400f0   R28 = 0000000000000001
        R13 = 00000000ada71900   R29 = 00000000ade5a300
        R14 = 00000000ac2185a8   R30 = 00000000f663f238
        R15 = 0000000000000004   R31 = 00000000f6624918
        pc  = c000000000050074 restore_gprs+0xc0/0x148
        cfar= c00000000004fe28 dont_restore_vec+0x1c/0x1a4
        lr  = 00000000b52a8184
        msr = 8000000100201030   cr  = 24804888
        ctr = 0000000000000000   xer = 0000000000000000   trap =  700
      
      This moves tm_recheckpoint to a C function and moves the tm_restore_sprs into
      that function.  It then adds IRQ disabling over the trechkpt critical section.
      It also sets the TEXASR FS in the signals code to ensure this is never set now
      that we explictly write the TM sprs in tm_recheckpoint.
      Signed-off-by: NMichael Neuling <mikey@neuling.org>
      cc: stable@vger.kernel.org
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      e6b8fd02
    • G
      powerpc/le: Enable RTAS events support · a08a53ea
      Greg Kurz 提交于
      The current kernel code assumes big endian and parses RTAS events all
      wrong. The most visible effect is that we cannot honor EPOW events,
      meaning, for example, we cannot shut down a guest properly from the
      hypervisor.
      
      This new patch is largely inspired by Nathan's work: we get rid of all
      the bit fields in the RTAS event structures (even the unused ones, for
      consistency). We also introduce endian safe accessors for the fields used
      by the kernel (trivial rtas_error_type() accessor added for consistency).
      
      Cc: Nathan Fontenot <nfont@linux.vnet.ibm.com>
      Signed-off-by: NGreg Kurz <gkurz@linux.vnet.ibm.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      a08a53ea
    • S
      powerpc: Correct emulated mtfsf instruction · c59c015b
      Stephen Chivers 提交于
      The emulated (CONFIG_MATH_EMULATION_FULL)
      PowerPC Floating Point instruction mtfsf
      does not correctly copy bits from its source
      register to the Floating Point Status and Register (FPSCR).
      
      The error is in the preparation of the mask used to
      select the bits to be copied from the source to the FPSCR.
      
      Execution of the mtfsf instruction does not produce the same
      results on a MPC8548 platform (emulated floating point)
      as on MPC7410 or 440EP platforms (hardware floating point).
      
      This error has been detected using a Freescale MPC8548
      based platform and the patch below tested using that platform.
      
      The patch is based on the patch(es) provided by
      Gabriel Paubert and analysis by Gabriel, James Yang and David Laight.
      Signed-off-by: NStephen Chivers <schivers@csc.com>
      Signed-off-by: NGabriel Paubert <paubert@iram.es>
      Tested-by: NStephen Chivers <schivers@csc.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      c59c015b
  2. 05 4月, 2014 22 次提交
  3. 04 4月, 2014 9 次提交