Place the UART gpio initialization inside the scb9328_init function as it is done on
other i.MX boards.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

As no flag is passed into UART0 platform data, pass NULL argument
when registering UART0.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

There are several occurences where MXC_INTERNAL_IRQ is
assumed to be the start of the gpio interrupts. It was never
meant this way. Replace these with gpio_to_irq.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NFabio Estevam <fabio.estevam@freescale.com>

This becomes meaningless in subsequent patches.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This becomes meaningless in subsequent patches.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

CONFIG_ARCH_* are deprecated, so remove one user.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

since we now can include all soc specific headers at once we do not
need the ifdeffery anymore.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

All soc specific header have proper namespace now and thus can
be included at once.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

We have a clocksource which renders CLOCK_TICK_RATE useless. Define
it to a bogus value to get rid of some ifdeffery.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This allows to move the led definition to .init.rodata.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This gets rid of per machine struct platform_device definitions and allows
to move the platform data and led definition to .init.rodata.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This gets rid of per machine struct platform_device definitions and allows
to move the platform data and led definition to .init.rodata.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Instead of using gpio_request followed by gpio_direction_output use gpio_request_array
when requesting multiple pins.

Also fixed the location of the delay for the reset and make the BABBAGE_USB_PHY_RESET to toggle.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The USB PHY Reset GPIO can be configured in the same place as the other GPIOs.

While at it rename the pin as BABBAGE_USB_PHY_RESET to make clearer its purpose.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

", o" was used for ", 0"

", 17" was used for ", 7 | 0x10"
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

dmaengine expects the maxburst parameter in words, not bytes.
The imxdma driver and its users do this wrong. Fix this.

As a side note the imx-pcm-dma-mx2 driver was 'fixed' to work
with imx-dma. This broke the driver with imx-sdma support which
correctly takes the maxburst parameter in words. This patch
puts the sdma based sound back to work.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The clock from which the I2C timing is derived is the ipg_perclk not ipg_clk.

I2C bus frequency was lower by a factor of ~8 due to the clock divider
calculation being based on 66.5MHz IPG clock while the bus actually
uses 8MHz ipg_perclk.

Kernel version: 3.0.0-rc2 branch 'imx-for-next' of git://git.pengutronix.de/git/imx/linux-2.6Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The pins are actually used (not in mainline yet):

	D4 -> SSP2_D0
	D5 -> GPIO
	D6 -> GPIO
	D7 -> GPIO for owire

so their pinmapping for SSP0 is wrong.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Fix below build error:
  CC      arch/arm/mach-mxs/devices/platform-mxsfb.o
arch/arm/mach-mxs/devices/platform-mxsfb.c: In function 'mx23_add_mxsfb':
arch/arm/mach-mxs/devices/platform-mxsfb.c:27: error: implicit declaration of function 'DMA_BIT_MASK'
make[2]: *** [arch/arm/mach-mxs/devices/platform-mxsfb.o] Error 1
make[1]: *** [arch/arm/mach-mxs/devices] Error 2
make: *** [arch/arm/mach-mxs] Error 2
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Tested-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Mark the actual interrupt source for some interrupts currently marked as reserved.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

iomux-v3.c uses NO_PAD_CTRL as a 32 bit value
so it should not be shifted left by MUX_PAD_CTRL_SHIFT(41)

Previously, anything requesting NO_PAD_CTRL would get
their pad control register set to 0.

Since it is a pad control mask, place it with the other mask values.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Acked-by: NLothar Waßmann <LW@KARO-electronics.de>
Tested-by: NLothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

On MX51 the address space length for SSI is 16KB.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The imx25 sdma script only gets TO1 version, so there is no need
to encode "to1" in the variable name.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The value 0 is not a valid TO version number.  With the current
code, imx-sdma driver will try to load firmware sdma-imx25-to0.bin,
which is obviously not a good name.  Instead, sdma-imx25-to1.bin
makes much more sense.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The sdma on soc imx25 is not a V1 but V2 block.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The sdma on all imx soc gets 16K IO space not 4K.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Fix the following warning:

CC      arch/arm/plat-mxc/iomux-v1.o
arch/arm/plat-mxc/iomux-v1.c: In function 'mxc_gpio_setup_multiple_pins':
arch/arm/plat-mxc/iomux-v1.c:160: warning: 'ret' may be used uninitialized in this function
arch/arm/plat-mxc/iomux-v1.c:160: note: 'ret' was declared here
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Fix the 2.8V (VMMC1) and 1.8V (VGEN) voltage generation on mx27_3ds.

Also configure the IOMUX for the PMIC interrupt pin and for the CSPI chip select that is connected
to the MC13783 PMIC.

In order to get the voltage for the LCD (2.8V and 1.8V) it is also necessary to turn on GPO1 and GPO3
supplies because they are connected to switches that enable these two voltages.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

When setting the IOMUX of multiple pins via mxc_gpio_setup_multiple_pins, gpio_request
is called and this prevents subsequent calls of gpio_request done by drivers to succeed.

Remove gpio_request call from mxc_gpio_setup_multiple_pins function.

As gpio_request is removed from mxc_gpio_setup_multiple_pins, there is no need to have
mxc_gpio_release_multiple_pins anymore, so remove this function.

Tested on a mx27_3ds board and after applying this patch it is possible to define all the
IOMUX setup in a static array
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Original code was assuming that the CSPI1 pins on the
MX31PDK were the primary pin function, which is incorrect.

On MX31PDK board these are the pins that provide CSPI1 functionality:

DSR_DCE1 (ALT mode 1) --> CSPI1_CLK
RI_DCE1 (ALT mode 1) --> CSPI1_RDY

DTR_DTE1  -->CSI1_MOSI
DSR_DTE1 --> CSPI1_MISO
DTR_DCE2 ---> CSPI1_SS2

The 3 IOMUX settings above are done via GPR as per Table A-1 of the MX31RM.

This patch fixes the CSPI1 IOMUX and makes the LCD to be functional.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

MX53 has 4 chip selects (CS0 - CS3) and the valid combinations are:

- CS0 (128MB)
- CS0 (64MB), CS1 (64MB)
- CS0 (64MB), CS1 (32MB), CS2 (32MB)
- CS0 (32MB), CS1 (32MB), CS2 (32MB) , CS3 (32MB)

Fix these addresses and also take into account all the four possibilities.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

MX53_PAD_PATA_DATA6 can have the following alternate modes:

PATA_DATA_6:  		mode 0
GPIO2_6:		mode 1
EMI_NANDF_D_6:		mode 3
ESDHC4_DAT6		mode 4
GPU3d_GPU_DEBUG_OUT_6	mode 5
IPU_DIAG_BUS_6		mode 6

Fix the modes accordingly.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NDinh Nguyen <dinh.nguyen@freescale.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Let USB Storage be built by default.

Also select NLS_ISO8859 so that the USB device can be mounted.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The patch fixes the warning below.

arch/arm/configs/mxs_defconfig:92:warning: symbol value 'm' invalid for RTC_CLASS
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Commit 13e12d14 ("vfs: reorganize 'struct inode' layout a bit")
moved things around a bit changed i_state to be unsigned int instead of
unsigned long.  That was to help structure layout for the 64-bit case,
and shrink 'struct inode' a bit (admittedly that only happened when
spinlock debugging was on and i_flags didn't pack with i_lock).

However, Meelis Roos reports that this results in unaligned exceptions
on sprc, and it turns out that the bit-locking primitives that we use
for the I_NEW bit want to use the bitops.  Which want 'unsigned long',
not 'unsigned int'.

We really should fix the bit locking code to not have that kind of
requirement, but that's a much bigger change.  So for now, revert that
field back to 'unsigned long' (but keep the other re-ordering changes
from the commit that caused this).

Andi points out that we have played games with this in 'struct page', so
it's solvable with other hacks too, but since right now the struct inode
size advantage only happens with some rare config options, it's not
worth fighting.

It _would_ be worth fixing the bitlocking code, though.  Especially
since there is no type safety in the bitlocking code (this never caused
any warnings, and worked fine on x86-64, because the bitlocks take a
'void *' and x86-64 doesn't care that deeply about alignment).  So it's
currently a very easy problem to trigger by mistake and never notice.
Reported-by: NMeelis Roos <mroos@linux.ee>
Cc: Andi Kleen <andi@firstfloor.org>
Cc: David Miller <davem@davemloft.net>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>