- 04 10月, 2012 1 次提交
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由 Anton Blanchard 提交于
There are a number of issues in the recent IOMMU pools code: - On a preempt kernel we might switch CPUs in the middle of building a scatter gather list. When this happens the handle hint passed in no longer falls within the local CPU's pool. Check for this and fall back to the pool hint. - We were missing a spin_unlock/spin_lock in one spot where we switch pools. - We need to provide locking around dart_tlb_invalidate_all and dart_tlb_invalidate_one now that the global lock is gone. Reported-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NAnton Blanchard <anton@samba.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> CC: <stable@kernel.org> [v3.6]
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- 27 9月, 2012 1 次提交
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由 Minghuan Lian 提交于
The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, some latest silicons do not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so change code to use 'Header Type' field to judge PCIE mode. Because FSL PCI controller does not support 'Header Type', patch still uses 'Programming Interface' to identify PCI mode. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 19 9月, 2012 2 次提交
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由 Jia Hongtao 提交于
Fix the following warning: arch/powerpc/sysdev/fsl_pci.c: In function 'fsl_pci_probe': arch/powerpc/sysdev/fsl_pci.c:867:25: error: unused variable 'hose' Signed-off-by: NJia Hongtao <B38951@freescale.com> Acked-by: NMichael Neuling <mikey@neuling.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Prabhakar Kushwaha 提交于
IFC may have one or two interrupts. If two interrupt specifiers are present, the first is the "common" interrupt (CM_EVTER_STAT), and the second is the NAND interrupt (NAND_EVTER_STAT). If there is only one, that interrupt reports both types of event. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 13 9月, 2012 8 次提交
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由 Jia Hongtao 提交于
We unified the Freescale pci/pcie initialization by changing the fsl_pci to a platform driver. In previous PCI code architecture the initialization routine is called at board_setup_arch stage. Now the initialization is done in probe function which is architectural better. Also It's convenient for adding PM support for PCI controller in later patch. Now we registered pci controllers as platform devices. So we combine two initialization code as one platform driver. Signed-off-by: NJia Hongtao <B38951@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Roy Zang 提交于
Freescale PCIe IP block revision bigger than rev2.2 will also need redefine the sequence of inbound windows. So change to use IP block revision instead of compatible for the judgment. Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Roy Zang 提交于
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Varun Sethi 提交于
All SOC device error interrupts are muxed and delivered to the core as a single MPIC error interrupt. Currently all the device drivers requiring access to device errors have to register for the MPIC error interrupt as a shared interrupt. With this patch we add interrupt demuxing capability in the mpic driver, allowing device drivers to register for their individual error interrupts. This is achieved by handling error interrupts in a cascaded fashion. MPIC error interrupt is handled by the "error_int_handler", which subsequently demuxes it using the EISR and delivers it to the respective drivers. The error interrupt capability is dependent on the MPIC EIMR register, which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error interrupt demuxing capability is dependent on the MPIC version and can be used for versions >= 4.1. Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NBogdan Hamciuc <bogdan.hamciuc@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Jia Hongtao 提交于
Remove the dependency on PCI initialization for SWIOTLB initialization. So that PCI can be initialized at proper time. SWIOTLB is partly determined by PCI inbound/outbound map which is assigned in PCI initialization. But swiotlb_init() should be done at the stage of mem_init() which is much earlier than PCI initialization. So we reserve the memory for SWIOTLB first and free it if not necessary. All boards are converted to fit this change. Signed-off-by: NJia Hongtao <B38951@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Acked-by: NTony Breeds <tony@bakeyournoodle.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Varun Sethi 提交于
Previously, these interrupts would be mapped, but the offset calculation was broken, and only the first group was initialized. Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Timur Tabi 提交于
The PCI controller on the Freescale P5040 is v2.4. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Tang Yuantian 提交于
The following platforms are supported: mpc8544, mpc8572, mpc8536, p1021, p1025, p1024, p1010. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 11 9月, 2012 2 次提交
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由 Arnd Bergmann 提交于
This cast is unneeded since *of_device_id.data became const. [ukl: split Arnd's patch by driver and add changelog] Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
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由 Uwe Kleine-König 提交于
This prepares *of_device_id.data becoming const. Without this change the following warning would occur: arch/powerpc/sysdev/fsl_msi.c: In function 'fsl_of_msi_probe': arch/powerpc/sysdev/fsl_msi.c:379:11: error: assignment discards 'const' qualifier from pointer target type [-Werror] Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
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- 05 9月, 2012 2 次提交
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由 Paul Mackerras 提交于
We have been observing hangs, both of KVM guest vcpu tasks and more generally, where a process that is woken doesn't properly wake up and continue to run, but instead sticks in TASK_WAKING state. This happens because the update of rq->wake_list in ttwu_queue_remote() is not ordered with the update of ipi_message in smp_muxed_ipi_message_pass(), and the reading of rq->wake_list in scheduler_ipi() is not ordered with the reading of ipi_message in smp_ipi_demux(). Thus it is possible for the IPI receiver not to see the updated rq->wake_list and therefore conclude that there is nothing for it to do. In order to make sure that anything done before smp_send_reschedule() is ordered before anything done in the resulting call to scheduler_ipi(), this adds barriers in smp_muxed_message_pass() and smp_ipi_demux(). The barrier in smp_muxed_message_pass() is a full barrier to ensure that there is a full ordering between the smp_send_reschedule() caller and scheduler_ipi(). In smp_ipi_demux(), we use xchg() rather than xchg_local() because xchg() includes release and acquire barriers. Using xchg() rather than xchg_local() makes sense given that ipi_message is not just accessed locally. This moves the barrier between setting the message and calling the cause_ipi() function into the individual cause_ipi implementations. Most of them -- those that used outb, out_8 or similar -- already had a full barrier because out_8 etc. include a sync before the MMIO store. This adds an explicit barrier in the two remaining cases. These changes made no measurable difference to the speed of IPIs as measured using a simple ping-pong latency test across two CPUs on different cores of a POWER7 machine. The analysis of the reason why processes were not waking up properly is due to Milton Miller. Cc: stable@vger.kernel.org # v3.0+ Reported-by: NMilton Miller <miltonm@bga.com> Signed-off-by: NPaul Mackerras <paulus@samba.org> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Michael Ellerman 提交于
These days they are just wrappers around __pa() and __va() respectively. Signed-off-by: NMichael Ellerman <michael@ellerman.id.au> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 24 8月, 2012 1 次提交
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由 Scott Wood 提交于
Add several #includes that mpic_msgr relies on being pulled implicitly, which only happens on certain configs. Signed-off-by: NScott Wood <scottwood@freescale.com> Cc: Meador Inge <meador_inge@mentor.com> Cc: Jia Hongtao <B38951@freescale.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 03 8月, 2012 1 次提交
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由 Jia Hongtao 提交于
We change fsl_add_bridge to return -ENODEV if the controller is working in agent mode. Then check the return value of fsl_add_bridge to guarantee that only successfully added host bus will be scanned. Signed-off-by: NJia Hongtao <B38951@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 27 7月, 2012 1 次提交
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由 Claudiu Manoil 提交于
The sram_offset parameter represents a physical address and should be of type phys_addr_t. As part of this fix, the extraction of sram_params is being cleaned-up and fixed. This patch fixes now the case when the offset value of 0xfff00000 was being rejected by the driver (returning -EINVAL), although this is a valid offset value. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 23 7月, 2012 1 次提交
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由 Benjamin Herrenschmidt 提交于
The current mpic code creates a linear revmap just big enough for all the sources, which happens to miss the IPIs and timers on some machines. This will in turn break when the irqdomain code loses the fallback of doing a linear search when the revmap fails (and really slows down IPIs otherwise). This happens for example on the U4 based Apple machines such as the dual core PowerMac G5s. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 11 7月, 2012 4 次提交
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由 Grant Likely 提交于
In preparation to remove the slow revmap path, eliminate the public radix revmap lookup functions. This simplifies the code and makes the slowpath removal patch a lot simpler. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com>
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由 Grant Likely 提交于
At irq_setup_virq() time all of the data needed to update the reverse map is available, but the current code ignores it and relies upon the slow path to insert revmap records. This patch adds revmap updating to the setup path so the slow path will no longer be necessary. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com>
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由 Scott Wood 提交于
As an alternative incremental starting point to Jia Hongtao's patchset, get the FSL PCI init out of the board files, but do not yet convert to a platform driver. Rather than having each board supply a magic register offset for determining the "primary" bus, we look for which PCI host bridge contains an ISA node within its subtree. If there is no ISA node, normally that would mean there is no primary bus, but until certain bugs are fixed we arbitrarily designate a primary in this case. Conversion to a platform driver and related improvements can happen after this, as the ordering issues are sorted out. Signed-off-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Stuart Yoder 提交于
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 10 7月, 2012 3 次提交
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由 Kokoris, Ioannis 提交于
QE Microcode Initialization using qe_upload_microcode() does not work on P1021 if the IRAM-Ready register is not set after the microcode upload. Add a definition for the "I-RAM Ready" register and sets it upon microcode upload completion. Signed-off-by: NIoannis Kokkoris <ioannis.kokoris@siemens-enterprise.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Varun Sethi 提交于
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC. This prevents us from eating in to hardware vector number space (MSIs) while setting up internal sources. Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Matias Garcia 提交于
Change quirk_fsl_pcie_header from __init to __devinit to ensure if we have a runtime access (like via an FPGA being loaded after boot on the PCIe link) that we dont access randomly freed memory. Signed-off-by: NMatias Garcia <mgarcia@rossvideo.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 17 6月, 2012 1 次提交
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The fixups are executed once the pci-device is found which is during boot process so __init seems fine as long as the platform does not support hotplug. However it is possible to remove the PCI bus at run time and have it rediscovered again via "echo 1 > /sys/bus/pci/rescan" and this will call the fixups again. Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: NSebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
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- 04 5月, 2012 1 次提交
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由 Josh Boyer 提交于
Fix a build error when -Werror is set: arch/powerpc/sysdev/ppc4xx_msi.c: In function ‘ppc4xx_setup_pcieh_hw’: arch/powerpc/sysdev/ppc4xx_msi.c:178:2: error: right shift count >= width of type [-Werror] Signed-off-by: NJosh Boyer <jwboyer@gmail.com>
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- 03 5月, 2012 1 次提交
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由 Mai La 提交于
This patch consists of: - Enable PCI MSI as default for Bluestone board - Change definition of number of MSI interrupts as it depends on SoC - Fix returning ENODEV as finding MSI node - Fix MSI physical high and low address - Keep MSI data logically Signed-off-by: NMai La <mla@apm.com> Signed-off-by: NJosh Boyer <jwboyer@gmail.com>
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- 30 4月, 2012 2 次提交
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由 Grant Likely 提交于
The switch from using irq_map to irq_alloc_desc*() for managing irq number allocations introduced new bugs in some of the powerpc interrupt code. Several functions rely on the value of NR_IRQS to determine the maximum irq number that could get allocated. However, with sparse_irq and using irq_alloc_desc*() the maximum possible irq number is now specified with 'nr_irqs' which may be a number larger than NR_IRQS. This has caused breakage on powermac when CONFIG_NR_IRQS is set to 32. This patch removes most of the direct references to NR_IRQS in the powerpc code and replaces them with either a nr_irqs reference or by using the common for_each_irq_desc() macro. The powerpc-specific for_each_irq() macro is removed at the same time. Also, the Cell axon_msi driver is refactored to remove the global build assumption on the size of NR_IRQS and instead add a limit to the maximum irq number when calling irq_domain_add_nomap(). Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Grant Likely 提交于
The mpc8xx driver uses a reference to NR_IRQS that is buggy. It uses NR_IRQs for the array size of the ppc_cached_irq_mask bitmap, but NR_IRQs could be smaller than the number of hardware irqs that ppc_cached_irq_mask tracks. Also, while fixing that problem, it became apparent that the interrupt controller only supports 32 interrupt numbers, but it is written as if it supports multiple register banks which is more complicated. This patch pulls out the buggy reference to NR_IRQs and fixes the size of the ppc_cached_irq_mask to match the number of HW irqs. It also drops the now-unnecessary code since ppc_cached_irq_mask is no longer an array. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 23 4月, 2012 2 次提交
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由 Benjamin Herrenschmidt 提交于
This gets rid of the unused default senses array, and replaces the incorrect use of IRQ_TYPE_NONE with the new IRQ_TYPE_DEFAULT for the initial set_trigger() call when mapping an interrupt. This in turn makes us read the HW state and update the irq desc accordingly. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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由 Benjamin Herrenschmidt 提交于
mpic_is_ipi() takes a virq and immediately converts it to a hw_irq. However, one of the two call sites calls it with a ... hw_irq. The other call site also happens to have the hw_irq at hand, so let's change it to just take that as an argument. Also change mpic_is_tm() for consistency. Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
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- 20 4月, 2012 2 次提交
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由 Mingkai Hu 提交于
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Mingkai Hu 提交于
Also fix issue of accessing invalid msgr pointer issue. The local msgr pointer in fucntion mpic_msgr_get will be accessed before getting a valid address which will cause kernel crash. Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 19 4月, 2012 1 次提交
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由 Paul Gortmaker 提交于
The following shows up in chroma_defconfig: CC arch/powerpc/sysdev/scom.o arch/powerpc/sysdev/scom.c: In function 'scom_debug_init': arch/powerpc/sysdev/scom.c:182:36: error: 'powerpc_debugfs_root' undeclared (first use in this function) arch/powerpc/sysdev/scom.c:182:36: note: each undeclared identifier is reported only once for each function it appears in make[2]: *** [arch/powerpc/sysdev/scom.o] Error 1 make[1]: *** [arch/powerpc/sysdev/scom.o] Error 2 A bisect leads to commit 9ffc93f2 "Remove all #inclusions of asm/system.h" Add the debug header which contains powerpc_debugfs_root. Acked-by: NDavid Howells <dhowells@redhat.com> Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
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- 29 3月, 2012 2 次提交
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由 Dave Liu 提交于
The MPC8569 Rev2.0 has the correct SNUM table as QE Reference Manual, we must follow it. However the Rev1.0 silicon need the old SNUM table as workaround due to Rev1.0 silicon SNUM erratum. So, we support both snum table, and choose the one FDT tell us. And u-boot will fixup FDT according to SPRN_SVR. Signed-off-by: NLiu Yu <yu.liu@freescale.com> Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 David Howells 提交于
Disintegrate asm/system.h for PowerPC. Signed-off-by: NDavid Howells <dhowells@redhat.com> Acked-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org> cc: linuxppc-dev@lists.ozlabs.org
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- 17 3月, 2012 1 次提交
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由 Vinh Nguyen Huu Tuong 提交于
This patch extends PCI-E driver to support PCI-E for APM821xx SoC on Bluestone board. Signed-off-by: NVinh Nguyen Huu Tuong <vhtnguyen@apm.com> Signed-off-by: NJosh Boyer <jwboyer@gmail.com>
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