1. 10 5月, 2010 4 次提交
    • M
      i7core: fix probing on Xeon55xx · 310cbb72
      Mauro Carvalho Chehab 提交于
      Xeon55xx fails to probe with this error message:
      
      EDAC DEBUG: in drivers/edac/i7core_edac.c, line at 1660: MC: drivers/edac/i7core_edac.c: i7core_init()
      EDAC i7core: Device not found: dev 00:00.0 PCI ID 8086:2c41
      i7core_edac: probe of 0000:00:14.0 failed with error -22
      
      This is due to the fact that, on Xeon35xx (and i7core), device 00.0 has
      PCI ID 8086:2c40.
      Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
      310cbb72
    • M
      i7core_edac: Add a code to probe Xeon 55xx bus · d1fd4fb6
      Mauro Carvalho Chehab 提交于
      This code changes the detection procedure of i7core_edac. Instead of
      directly probing for MC registers, it probes for another register found
      on Nehalem. If found, it tries to pick the first MC PCI BUS. This should
      work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255
      that are not properly detected by the non-legacy PCI methods.
      
      The new detection code scans specifically at buses 254 and 255 for the
      Xeon 55xx devices.
      
      This code has not tested yet. After working, a change at the code will
      be needed, since the i7core is not yet ready for working with 2 sets of
      MC.
      Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
      d1fd4fb6
    • M
      i7core_edac: Adds write unlock to MC registers · e9bd2e73
      Mauro Carvalho Chehab 提交于
      The public Intel Xeon 5500 volume 2 datasheet describes, on page 53,
      session 2.6.7 a register that can lock/unlock Memory Controller the
      configuration register, called MC_CFG_CONTROL.
      
      Adds support for it in the hope that software error injection would
      work. With my tests with Xeon 35xx, there's still something missing.
      With a program that does sequencial bit writes at dev 0.0, sometimes, it
      produces error injection, after unblocking the MC_CFG_CONTROL (and,
      sometimes, it just locks my testing machine).
      
      I'll try later to discover by trial and error what's the register that
      solves this issue on Xeon 35xx.
      Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
      e9bd2e73
    • M
      i7core_edac: Add an EDAC memory controller driver for Nehalem chipsets · a0c36a1f
      Mauro Carvalho Chehab 提交于
      This driver is meant to support i7 core/i7core extreme desktop
      processors and Xeon 35xx/55xx series with integrated memory controller.
      It is likely that it can be expanded in the future to work with other
      processor series based at the same Memory Controller design.
      
      For now, it has just a few MCH status reads.
      Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
      a0c36a1f
  2. 03 3月, 2010 2 次提交
  3. 25 2月, 2010 1 次提交
  4. 23 2月, 2010 1 次提交
  5. 05 12月, 2009 1 次提交
  6. 04 12月, 2009 1 次提交
  7. 21 11月, 2009 1 次提交
  8. 12 11月, 2009 1 次提交
  9. 07 11月, 2009 1 次提交
  10. 29 10月, 2009 2 次提交
  11. 24 10月, 2009 1 次提交
  12. 16 10月, 2009 1 次提交
  13. 08 10月, 2009 1 次提交
  14. 19 9月, 2009 1 次提交
  15. 18 9月, 2009 1 次提交
  16. 11 9月, 2009 2 次提交
  17. 10 9月, 2009 1 次提交
  18. 09 9月, 2009 1 次提交
  19. 02 9月, 2009 1 次提交
    • B
      powerpc: Fix some late PowerMac G5 with PCIe ATI graphics · cede3930
      Benjamin Herrenschmidt 提交于
      A misconfiguration by the firmware of the U4 PCIe bridge on PowerMac G5
      with the U4 bridge (latest generations, may also affect the iMac G5
      "iSight") is causing us to re-assign the PCI BARs of the video card,
      which can get it out of sync with the firmware, thus breaking offb.
      
      This works around it by fixing up the bridge configuration properly
      at boot time. It also fixes a bug where the firmware provides us with
      an incorrect set of accessible regions in the device-tree.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      cede3930
  20. 30 8月, 2009 1 次提交
  21. 13 8月, 2009 1 次提交
  22. 01 7月, 2009 1 次提交
    • M
      parport/serial: add support for NetMos 9901 Multi-IO card · c4285b47
      Michael Buesch 提交于
      Add support for the PCI-Express NetMos 9901 Multi-IO card.
      
      0001:06:00.0 Serial controller [0700]: NetMos Technology Device [9710:9901] (prog-if 02 [16550])
              Subsystem: Device [a000:1000]
              Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
              Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
              Latency: 0, Cache Line Size: 64 bytes
              Interrupt: pin A routed to IRQ 65
              Region 0: I/O ports at 0030 [size=8]
              Region 1: Memory at 80105000 (32-bit, non-prefetchable) [size=4K]
              Region 4: Memory at 80104000 (32-bit, non-prefetchable) [size=4K]
              Capabilities: <access denied>
              Kernel driver in use: serial
              Kernel modules: 8250_pci
      
      0001:06:00.1 Serial controller [0700]: NetMos Technology Device [9710:9901] (prog-if 02 [16550])
              Subsystem: Device [a000:1000]
              Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
              Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
              Latency: 0, Cache Line Size: 64 bytes
              Interrupt: pin B routed to IRQ 65
              Region 0: I/O ports at 0020 [size=8]
              Region 1: Memory at 80103000 (32-bit, non-prefetchable) [size=4K]
              Region 4: Memory at 80102000 (32-bit, non-prefetchable) [size=4K]
              Capabilities: <access denied>
              Kernel driver in use: serial
              Kernel modules: 8250_pci
      
      0001:06:00.2 Parallel controller [0701]: NetMos Technology Device [9710:9901] (prog-if 03 [IEEE1284])
              Subsystem: Device [a000:2000]
              Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
              Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
              Latency: 0, Cache Line Size: 64 bytes
              Interrupt: pin C routed to IRQ 65
              Region 0: I/O ports at 0010 [size=8]
              Region 1: I/O ports at <unassigned>
              Region 2: Memory at 80101000 (32-bit, non-prefetchable) [size=4K]
              Region 4: Memory at 80100000 (32-bit, non-prefetchable) [size=4K]
              Capabilities: <access denied>
              Kernel driver in use: parport_pc
              Kernel modules: parport_pc
      
      [   16.760181] PCI parallel port detected: 416c:0100, I/O at 0x812010(0x0), IRQ 65
      [   16.760225] parport0: PC-style at 0x812010, irq 65 [PCSPP,TRISTATE,EPP]
      [   16.851842] serial 0001:06:00.0: enabling device (0004 -> 0007)
      [   16.883776] 0001:06:00.0: ttyS0 at I/O 0x812030 (irq = 65) is a ST16650V2
      [   16.893832] serial 0001:06:00.1: enabling device (0004 -> 0007)
      [   16.926537] 0001:06:00.1: ttyS1 at I/O 0x812020 (irq = 65) is a ST16650V2
      Signed-off-by: NMichael Buesch <mb@bu3sch.de>
      Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      c4285b47
  23. 16 6月, 2009 1 次提交
    • S
      USB: xhci: BIOS handoff and HW initialization. · 66d4eadd
      Sarah Sharp 提交于
      Add PCI initialization code to take control of the xHCI host controller
      away from the BIOS, halt, and reset the host controller.  The xHCI spec
      says that BIOSes must give up the host controller within 5 seconds.
      
      Add some host controller glue functions to handle hardware initialization
      and memory allocation for the host controller.  The current xHCI
      prototypes use PCI interrupts, but the xHCI spec requires MSI-X
      interrupts.  Add code to support MSI-X interrupts, but use the PCI
      interrupts for now.
      Signed-off-by: NSarah Sharp <sarah.a.sharp@linux.intel.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      66d4eadd
  24. 14 6月, 2009 1 次提交
  25. 11 6月, 2009 1 次提交
  26. 07 6月, 2009 1 次提交
  27. 25 5月, 2009 2 次提交
  28. 22 5月, 2009 1 次提交
  29. 19 5月, 2009 2 次提交
  30. 14 5月, 2009 1 次提交
  31. 23 4月, 2009 1 次提交
  32. 14 4月, 2009 1 次提交